Winter 2022 - ECE2700: Digital Logic Design

Winter 2022 - ECE2700: Digital Logic Design

Unit 1: Introduction to Logic Circuits

Lecture Notes - Unit 1
Videos (live lectures): (01/07/2021)
Videos (narrated lectures):
- Canonical Forms, Timing Diagrams, Digital Design
- VHDL: logic gates, testbench generation
Videos: VHDL coding, synthesis, and simulation in Vivado:
- Experiment: First VHDL Example + I/O Assignments and programming on Nexys A7-50T Board

Unit 2: Optimized Implementation of Logic Functions

Lecture Notes - Unit 2
Videos (live lectures): (01/14/2021)
Videos: VHDL coding, synthesis, and simulation in Vivado:
- Experiment: 4-bit Adder description in VHDL + I/O Assignments on Nexys A7-50T

Unit 3: Implementation Technology

Unit 4: Number Systems and Computer Arithmetic

Unit 5: Combinational Circuits

Unit 6: Synchronous Sequential Circuits

Unit 7: Introduction to Digital System Design

Homeworks, Quizzes, Exams

LABORATORY

Hardware:
- Nexys^TM A7 FPGA Trainer Board - Option A7-50T (which houses the XCA750T-1CSG324I Artix-7 FPGA): webpage
- Nexys A7 FPGA Trainer Board Schematics
- Nexys A7 FPGA Trainer Board Reference Manual
- Nexys A7-50T FPGA Trainer Board Master XDC file for Vivado Designs
- Nexys A7-100T FPGA Trainer Board Master XDC file for Vivado Designs
- Basys 3 Trainer Board (which houses the XC7A35T-1CPG236C Artix-7 FPGA): webpage
- Basys 3 Trainer Board Schematics
- Basys 3 Trainer Board Reference Manual
- Basys 3 Trainer Board Master XDC file for Vivado Designs
- Nexys^TM-4 DDR Artix-7 FPGA Board (which houses the XC7A100T-1CSG324 Artix-7 FPGA) - Legacy Board
- Nexys-4 DDR Schematics
- Nexys-4 DDR Reference Manual
- Nexys-4 DDR Master XDC file for Vivado Designs

Software: Xilinx Vivado ML Standard Edition (previously known as Webpack Edition): Download

Laboratory Assignments

FINAL PROJECT

List of Projects

Reconfigurable Computing Research Laboratory (RECRLab), Electrical and Computer Engineering Department, Oakland University