Unit 1: Introduction

• Slides
• Step-by-step video: VHDL coding + Synthesis + Simulation in Vivado:
  • 3-input logic function + I/O assignment and programming (Nexys A7-50T)

VHDL Projects (VHDL file, testbench, and XDC file):

• Example (XDC included): (Project)
• Light Control (XDC included): (Project)
• Security combination (XDC included): (Project)

VHDL Projects (VHDL file, testbench, and UCF file):

• Example (UCF included): (Project)
• Light Control (UCF included): (Project)
• Security combination (UCF included): (Project)

Unit 2: Concurrent Description

• Slides

VHDL Projects (VHDL file, testbench, and XDC file):

• 3-to-8 Decoder (XDC included): (Project)
• 1-to-8 Demultiplexor (XDC included): (Project)
• 8-bit Bi-directional Port (XDC included): (Project)
• 4-bit adder/subtractor (XDC included): (Project)

VHDL Projects (VHDL file, testbench):

• 4-to-1 LUT: (Project)
• 7-segment decoder (UCF included): (Project)
• Priority encoder: 8-to-3 (UCF included): (Project)
• 4-to-1 Bus Mux (2 styles): (Project)
• Tri-state Buffer (UCF included): (Project)
• Bi-directional Port (4 bits): (Project)

Unit 3: Behavioral Description

• Slides
• Video: Asynchronous processes for combinational circuits (VHDL)

VHDL Projects (VHDL file, testbench, and XDC file):

• N-bit Absolute value of A-B (A,B: unsigned): (Project)
• Priority encoder: 8-to-3 (XDC included): (Project)

VHDL Projects (VHDL file, testbench):

• Majority Gate (TMR): (Project)
• 2-to-4 decoder (3 styles) (UCF included): (Project)
• Zeros/Ones Detector (UCF included): (Project)

Unit 4: Structural Description

• Slides
• Step-by-step videos: VHDL coding + Synthesis + Simulation in Vivado:
  • 4-bit adder (unsigned) + I/O assignment (Nexys A7-50T)
  • 4-bit subtractor (unsigned)

VHDL Projects (VHDL file, testbench, and XDC file):

• 4-to-16 Decoder (XDC included): (Project)
• Generic Adder (XDC included): (Project)
• Generic 2's complement Adder/Subtractor Unit (XDC included): (Project) (VHDL main file)

VHDL Projects (VHDL file, testbench):

• Arithmetic Logic Unit (ALU): (Project)
• 6-to-6 Look-up Table (UCF included) (Project)
• 16-to-4 priority encoder. Result shown in 7-segment display (UCF included) (Project)
• 7-segment display control: Only one display is ON at any time (UCF included) (Project)

Unit 5: Sequential Circuits

• Slides
• Counter modulo-N (generic pulse generator) with enable and synchronous clear: Report

VHDL Projects (VHDL file, testbench, and XDC file):

• D-type flip flop with enable: (VHDL file)
• D-type flip flop with enable and synchronous clear: (VHDL file)
• N-bit register with enable and synchronous clear: (Project) (VHDL file)
• Counter modulo-N (generic pulse generator) with enable and synchronous clear: (Project) (VHDL file)
• N-bit Parallel access (right/left) shift register with enable and synchronous clear: (Project) (VHDL file)
• N-bit Ring counter: (Project) (VHDL main file)
• N-bit Johnson counter: (Project) (VHDL main file)
• BCD up/down counter with enable and Rate Control (XDC included): (Project)

VHDL Projects (VHDL file, testbench):

• Modulo-13 counter with enable: (Project)
• BCD up/down counter with enable: (Project)
• Counter modulo-N (Generic pulse generator) with enable: (Project) (VHDL file)
• N-bit (right/left) shift register with enable: (Project) (VHDL file)
• N-bit Parallel access (right/left) shift register with enable: (Project) (VHDL file)
• LUT6to6 peripheral with 3-state buffers: (Project)

Unit 6: Finite State Machines

• Slides
• FSMs (ECE2700): Notes
• Video: explanation + VHDL coding:
  • ASMs, VHDL description (sequence detector)
  • ASM Chart example, VHDL description (Arbiter)

VHDL Projects (VHDL file, testbench, and XDC file):

• Pulse detector: (Project)
• 3-input Arbiter: (Project) (VHDL file)

VHDL Projects (VHDL files, testbench):

• 2-bit counter (FSM): (Project)
• BCD counter with stop signal (FSM): (Project)
• Sequence detector (FSM): (Project)
• LED sequence (FSM): (Project)

Unit 7: Digital System Design

• Slides
• Digital Systems (ECE2700): Notes
• VGA Display Control: Report
• Step-by-step videos: VHDL coding + Synthesis + Simulation on Vivado:
  • Bit-Counting circuit (n=8)
  • Sequential multiplier nxn (n=4)
• Video: VHDL: Embedding counters, registers, shift registers in ASMs

VHDL Projects (VHDL file, testbench, and XDC file):

• Bit Counting Circuit for N-bit input: (Project)
• Integer Base-2 Logarithm for N-bit input: (Project)
• Generic Sequential Multiplier (NxN, unsigned): (Project) (VHDL main file)
• Digital Stopwatch (XDC included): (Project) (VHDL main file)
• Binary to BCD Algorithm: (Project)
• Debouncing Circuit: (Project)
• Interfacing circuits:
  • UART Tx (XDC included): (Project)
  • PS/2 Keyboard Controller (XDC included): (Project)
  • 7-segment serializer (four displays): (XDC included): (Project)
  • VGA Display Control (XDC included): (Project) (MATLAB file [image to txt]) (test picture)
• ADXL362 Accelerometer (SPI) - Basic Control (XDC included): (Project) (ADXL362 datasheet)
• ADT7420 Temp. Sensor (I2C) - Basic Control (XDC included): (Project) (ADT7420 datasheet)
• PWM Control (Period: parameter, DC: 0 to Period): (Project)
  • PWM: RGB Color Control. 4 bits per color component (XDC included): (Project)
  • PWM: Tone control. Mono audio output with Low-Pass Filter (XDC included): (Project)
• Simple Example of Digital System. Two approaches:
  • Direct: ASM diagram coding with counters/registers instantiation: (digsys_ex.zip)
  • Embedding counters/registers embedded in ASM diagram: (digsys_exp.zip)

VHDL Projects (VHDL files, testbench):

• Lights pattern (UCF included): (Project) (VHDL main file)
• UART Tx (UCF included): (Project)
• Generic Accumulator: (Project) (VHDL main file)

Unit 8: Parameterization, custom-defined arrays

• Slides

VHDL Projects (VHDL file, testbench):

• Counter modulo-N with enable, synchronous clear, up/down control, and output comparator: (Project)
• N-bit Parallel access (right/left) shift register with enable and synchronous clear - Structural version: (Project)
• N-bit Absolute value of A-B (A,B: signed/unsigned): (Project)
• Generic Array Unsigned Multiplier: NxN bits (XDC included): (Project) (VHDL main file)
• N-bit Barrel Shifter (ARITHMETIC, LOGICAL, ROTATION modes):
  • Distance constrained from 0 to N-1: (Project)
  • Unconstrained distance: (Project)
• N-bit Johnson/Ring Counter: (Project)
• N-bit signed/unsigned combinational multiplier: (Project)
• Vector MUX - 2 styles:
  • Input: std_logic_vector: NxB bits: (Project)
  • Input: std_logic_2d: NxB bits: (Project)
• Vector DEMUX: N B-bit outputs: (Project)
• Vector Parallel Access Shift Register: (Project)
• LFSR (Linear Feed Back Shift Registers):
  • CRC (Cyclic Redundancy Check), N-bits: (Project)
  • MIC (Multiple-input Compressor), N-bits: (Project)
• Multi-digit (N digits) BCD Adder: (Project)
• NxN Convolution Kernel - Pipelined: (Project)

VHDL Projects (VHDL files, testbench):

• N-bit Tri-state Buffer: (Project)
• N-bit Binary to Gray converter: (Project)
• Mux N-to-1: (Project)

Unit 9: Miscelaneous Topics: I/O Text files, FPGA Resources

• Slides

VHDL Projects (VHDL file, testbench, and XDC file):

• NC NI-to-NO LUTs with I/O Registers: (Project)
• FPGA Resources:
  • BRAMs (Artix-7 FPGA or 7-series PL): Generic 16-bit memory (single port) for 2-D data: (in_RAMgen.vhd) (Test text file)
  • MMCMs (Artix-7 FPGA or 7-series PL): Frequency synthesizer (3 output clocks with programmable frequency): (MMCM_wrapper.vhd) (Testbench)

...