Winter 2023 - ECE4710/ECE5710: Computer Hardware Design

Winter 2023 - ECE4710/5710: Computer Hardware Design

Syllabus
For background on Digital Logic Design, see Fall 2021 - Digital Logic Design Class
For VHDL on FPGAs material, see Tutorial: VHDL for FPGAs
Useful links:
- VHDL examples for Nexys-3 Board: VHDL Workshop
- Prof. Hanna's book: Introduction to Digital Design Using Digilent FPGA Boards - Block Diagram/VHDL Examples

Unit 1: Digital System Design

Lecture Notes - Unit 1
Videos (live lectures): (01/07/2021) (01/14/2021)
Videos (narrated lectures):

Unit 2: Computer Arithmetic

Lecture Notes - Unit 2
Videos (live lectures): (01/21/2021) (01/28/2021) (02/04/2021)
Videos (narrated lectures):

Unit 3: External Peripherals: Interfacing

Unit 4: Special-Purpose Circuits and Techniques

Lecture Notes - Unit 4
Videos (live lectures): (03/04/2021) (03/11/2021)
Videos (narrated lectures):
- VHDL: Simulation - reading/writing text files
- VHDL: Synthesis - reading input text files

Unit 5: Pipelining and unfolding

Lecture Notes - Unit 5
Videos (narrated lectures):
- Pipelining and unfolding: explanation
- Pipelining and unfolding: example

Unit 6: Microprocessor Design

Lecture Notes - Unit 6
- PicoBlaze^TM User Guide (Xilinx)
Videos (live lectures): (03/18/2021) (03/25/2021) (04/01/2021) (04/08/2021)
Videos (narrated lectures):

Homeworks, Exams

Homework 1

Solutions - Homework 1

Homework 2

Solutions - Homework 2

MIDTERM Exam

Solutions - MIDTERM Exam

Homework 3

Solutions - Homework 3 SolutionsHW3p1.zip

Homework 4

Solutions - Homework 4

LABORATORY

Hardware:
- Nexys^TM A7 FPGA Trainer Board - Option A7-50T (which houses the XCA750T-1CSG324I Artix-7 FPGA): webpage
- Nexys A7 FPGA Trainer Board Schematics
- Nexys A7 FPGA Trainer Board Reference Manual
- Nexys A7-50T FPGA Trainer Board Master XDC file for Vivado Designs
- Nexys A7-100T FPGA Trainer Board Master XDC file for Vivado Designs
- Nexys^TM-4 DDR Artix-7 FPGA Board (which houses the XC7A100T-1CSG324 Artix-7 FPGA) - Legacy Board
- Nexys-4 DDR Schematics
- Nexys-4 DDR Reference Manual
- Nexys-4 DDR Master XDC file for Vivado Designs

Software: Xilinx Vivado ML Standard Edition (previously known as Webpack Edition): Download

Laboratory Assignments

Laboratory 1 mydebouncer.vhd my_genpulse_sclr.vhd
Laboratory 2 mybarrelshift_gen.vhd myLZD.vhd
Laboratory 3 accelerom.zip (ADXL362 datasheet)
Laboratory 4 in_RAMgen.vhd myinival.txt fsm_sclk.vhd my_genpulse_sclr.vhd
Laboratory 5 in_benchR_100.txt in_benchV_100.txt
Laboratory 6 lab6files.zip mydebouncer.vhd my_genpulse_sclr.vhd mypulse_det.vhd MMCM_wrapper.vhd

FINAL PROJECT

List of Projects

Security System: Report Presentation
Ping Pong Game: Report Presentation
Temperature-controlled Fan: Report Presentation
K-Line communication: Report Presentation
CAN communication: Report Presentation

Reconfigurable Computing Research Laboratory (RECRLab), Electrical and Computer Engineering Department, Oakland University