Embedded System Design for Zynq SoC

Tutorials Vivado projects for the ZYBO Board

Unit 1: Introduction to Vivado

Vivado Project (VHDL files, testbench, and XDC file):

  • BCD Up/Down Counter with rate control: (Project)

Unit 2: Introduction to Hardware/Software Design

Vivado/SDK Project (XDC, XML, and .c files):

Unit 3: AXI4-Lite: Custom Peripheral

Vivado/SDK Projects (.vhd, .c., and .txt files):

  • Pixel Processor project: (.zip)
  • Pipelined Divider project: (.zip)
  • Pipelined 2D Convolution Kernel project: (.zip)

Unit 4: AXI4-Full: Custom Peripheral

Vivado/SDK Projects (.vhd, .c, and .txt files):

  • Pixel Processor (Full AXI) project: (.zip)
  • Pipelined Divider (Full AXI) project: (.zip)
  • 2-D DCT (Full AXI) project: (.zip)

Unit 5: SD Card

SDK Project files (.c, .h) and MATLAB script:

Unit 6: Dynamic Partial Reconfiguration - Only PL using JTAG

PR Projects (VHDL files, .xdc file, TCL files):

  • 4-bit LED Pattern controller (1 RP) for ZYBO Board: (.zip)
  • 4-bit LED Pattern controller (2 RPs) for ZYBO Board: (.zip)

Unit 7: Dynamic Partial Reconfiguration - PS+PL system using PCAP

PR Projects (VHDL files, .xdc files, TCL files, .c files):

  • Pixel Processor (1 RP, vary function): (.zip)
  • DCT 2D (1 RP, vary Transform size): (.zip) (verified in Vivado 2017.3 as well)

Unit 8: Using DMA

SDK Project files (.c):

Unit 9: Using PL Interrupts

Vivado/SDK Projects (.vhd, .c, and .txt files)::

  • Pixel Processor with Interrupt output(AXI4-Full) project: (.zip)





This material is based upon work supported by the National Science Foundation under NSF AWD CNS-1422031. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.


Reconfigurable Computing Research Laboratory (RECRLab), Electrical and Computer Engineering Department, Oakland University