VHDL Coding for FPGAs


Slides and Notes Xilinx Vivado 2016.2 projects for the NexysTM-4 DDR Artix-7 FPGA Board Xilinx ISE 14.7 projects for the NexysTM-4 Artix-7 FPGA Board

Unit 1: Introduction

VHDL Projects (VHDL file, testbench, and XDC file):

VHDL Projects (VHDL file, testbench, and UCF file):

Unit 2: Concurrent Description

VHDL Projects (VHDL file, testbench, and XDC file):

  • 3-to-8 Decoder (XDC included): (Project)
  • 1-to-8 Demultiplexor (XDC included): (Project)
  • 8-bit Bi-directional Port (XDC included): (Project)
  • 4-bit adder/subtractor (XDC included): (Project)

VHDL Projects (VHDL file, testbench):

Unit 3: Behavioral Description

VHDL Projects (VHDL file, testbench, and XDC file):

  • N-bit Absolute value of A-B (A,B: unsigned): (Project)
  • Priority encoder: 8-to-3 (XDC included): (Project)

VHDL Projects (VHDL file, testbench):

Unit 4: Structural Description

VHDL Projects (VHDL file, testbench, and XDC file):

VHDL Projects (VHDL file, testbench):

Unit 5: Sequential Circuits

  • Slides
  • Generic Pulse Generator (or Counter modulo-N): Report

VHDL Projects (VHDL file, testbench, and XDC file):

VHDL Projects (VHDL file, testbench):

Unit 6: Finite State Machines

VHDL Projects (VHDL file, testbench, and XDC file):

VHDL Projects (VHDL files, testbench):

Unit 7: Digital System Design

VHDL Projects (VHDL file, testbench, and XDC file):

VHDL Projects (VHDL files, testbench):

Unit 8: Parameterization, custom-defined arrays

VHDL Projects (VHDL file, testbench):

  • Counter modulo-N with enable, synchronous clear, up/down control, and output comparator: (Project)
  • N-bit Parallel access (right/left) shift register with enable and synchronous clear - Structural version: (Project)
  • N-bit Absolute value of A-B (A,B: signed/unsigned): (Project)
  • N-bit Barrel Shifter (ARITHMETIC, LOGICAL, ROTATION modes):
  • N-bit Johnson/Ring Counter: (Project)
  • Vector MUX - 2 styles:
  • Vector DEMUX: N B-bit outputs: (Project)
  • LFSR (Linear Feed Back Shift Registers):
    • CRC (Cyclic Redundancy Check), N-bits: (Project)
    • MIC (Multiple-input Compressor), N-bits: (Project)
  • Multi-digit (N digits) BCD Adder: (Project)
  • NxN Convolution Kernel - Pipelined: (Project)

VHDL Projects (VHDL files, testbench):

Unit 9: Miscelaneous Topics: I/O Text files, FPGA Resources

VHDL Projects (VHDL file, testbench, and XDC file):

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Acknowledgments

This material is based upon work supported by the National Science Foundation under NSF AWD CNS-1422031. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.

 


Reconfigurable Computing Research Laboratory (RECRLab), Electrical and Computer Engineering Department, Oakland University