IMAGE AND VIDEO PROCESSING ON ALTERA DE2-115 USING NIOS II SOFT-CORE PROCESSOR
Term Project for ECE 576 Embedded System Design with FPGA
Fall 2014 Semester
By
Michael Barker, Master Student, MS in Electrical Engineering
Manaswi Yarradoddi, Master Student, MS in Electrical Engineering
Roshini Naidu, Master Student, MS in Embedded Systems
Advisor: Prof. Subramaniam Ganesan
Introduction:
Click here to Download Presentation in pdf format
Image and video processing are used widely in automotive multimedia applications. Examples of such applications are navigation aids and driver information systems.
For the design project for this class we proposed to change the background of the image captured by the camera and displaying it on the Multi-Touch LCD screen. The goal of the project was to write a VHDL program that would connect a digital camera and a Multi- touch screen display to an FPGA board and capture live video from the digital camera. The captured image is then displayed on the touch screen display. Touching the image and bouncing and zooming it, moving it up and down, Right and left,diminishing the image and enlarging it. The hardware components necessary to develop such a project are a camera, LCD screen and Altera board.
The project utilizes the following hardware:
- Altera Video and Embedded Evaluation Kit
- Multi-touch (VEEK-MT) which includes:
- Altera DE2-115 FPGA development board.
- Digital camera.
- Multi-Touch LCD touch panel development kit.
- Altera Cyclone IV 4CE115 FPGA device
- Altera Serial Configuration device – EPCS64
- USB Blaster (on board) for programming; both JTAG and Active Serial (AS) programming modes are supported
- 2MB SRAM
- Two 64MB SDRAM
- 8MB Flash memory
- SD Card socket
- 4 Push-buttons
- 18 Slide switches
- 18 Red user LEDs
- 9 Green user LEDs
- 50MHz oscillator for clock sources
- 24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks
- VGA DAC (8-bit high-speed triple DACs) with VGA-out connector
- TV Decoder (NTSC/PAL/SECAM) and TV-in connector
- 2 Gigabit Ethernet PHY with RJ45 connectors
- USB Host/Slave Controller with USB type A and type B connectors
- RS-232 transceiver and 9-pin connector
- PS/2 mouse/keyboard connector
- IR Receiver
- 2 SMA connectors for external clock input/output
- One 40-pin Expansion Header with diode protection
- One High Speed Mezzanine Card (HSMC) connector
- 16x2 LCD module
- Cyclone IV EP4CE115F29 device
- 114,480 LEs
- 432 M9K memory blocks
- 3,888 Kbits embedded memory
- 4 PLLs
- JTAG and AS mode configuration
- EPCS64 serial configuration device
- On-board USB Blaster circuitry
- 128MB (32Mx32bit) SDRAM
- 2MB (1Mx16) SRAM
- 8MB (4Mx16) Flash with 8-bit mode
- 32Kb EEPROM
- Provides SPI and 4-bit SD mode for SD Card access
- Two Ethernet 10/100/1000 Mbps ports
- High Speed Mezzanine Card (HSMC)
- Configurable I/O standards (voltage levels:3.3/2.5/1.8/1.5V)
- USB type A and B o Provide host and device controllers compliant with USB 2.0
- Support data transfer at full-speed and low-speed o PC driver available
- 40-pin expansion port
- Configurable I/O standards (voltage levels:3.3/2.5/1.8/1.5V)
- VGA-out connector
- VGA DAC (high speed triple DACs)
- DB9 serial connector for RS-232 port with flow control
- PS/2 mouse/keyboard
- Three 50MHz oscillator clock inputs
- SMA connectors (external clock input/output)
- 24-bit encoder/decoder (CODEC)
- Line-in, line-out, and microphone-in jacks
- 16x2 LCD module
- 18 slide switches and 4 push-buttons switches
- 18 red and 9 green LEDs
- Eight 7-segment displays
- Infrared remote-control receiver module
- TV decoder (NTSC/PAL/SECAM) and TV-in connector
- Desktop DC input
- Switching and step-down regulators LM3150MH
SYSTEM BLOCK DIAGRAM
The constant reduction both of cost and size of image sensors and the increasing complexity of FPGA circuits let us to design and implement an FPGA-based Digital Camera System. Also, due to the appearance of the LCD Touch Panels this system could be able to be controlled from such a panel. Furthermore, the flexibility of FPGAs gives us the possibility to integrate additional applications and image processing algorithms to the system without any cost in hardware. It’s worth mentioning that the hardware image processing algorithms could be faster than the corresponding algorithms in C/C++.
For the implementation of this system the development platform DE2 by Altera, the TRDB-D5M Camera and the TRDB-LTM LCD Touch Panel by Terasic have been chosen. Some of the DE2’s I/Os have been used for the interconnection of the Camera and the LCD Touch Panel as well as for the communication between the DE2 and a PC.
Hardware
Altera DE2-115 Board
The Altera® DE2-115 Development and Education board was designed by professors, for professors. It is an ideal vehicle for learning about digital logic, computer organization, and FPGAs. Featuring an Altera Cyclone® IV 4CE115 FPGA, the DE2-115 board is designed for university and college laboratory use. It is suitable for a wide range of exercises in courses on digital logic and computer organization, from simple tasks that illustrate fundamental concepts to advanced designs.
The DE2 series has consistently been at the forefront of educational development boards by distinguishing itself with an abundance of interfaces to accommodate various application needs. Extending its leadership and success, Terasic announces the latest DE2-115 that features the Cyclone IV E device. Responding to increased versatile low-cost spectrum needs driven by the demand for mobile video, voice, data access, and the hunger for high-quality images, the new DE2-115 offers an optimal balance of low cost, low power and a rich supply of logic, memory and DSP capabilities.The Cyclone EP4CE115 device equipped on the DE2-115 features 114,480 logic elements (LEs), the largest offered in the Cyclone IV E series, up to 3.9-Mbits of RAM, and 266 multipliers. In addition, it delivers an unprecedented combination of low cost and functionality, and lower power compared to previous generation Cyclone devices.The DE2-115 adopts similar features from the earlier DE2 series primarily the DE2-70, as well as additional interfaces to support mainstream protocols including Gigabit Ethernet (GbE). A High-Speed Mezzanine Card (HSMC) connector is provided to support additional functionality and connectivity via HSMC daughter cards and cables. For large-scale ASIC prototype development, a connection can be made with two or more FPGA-based boards by means of a HSMC cable through the HSMC connector.
The following pictures depicts the layout of the board and indicates the location of the connectors and key components:
The DE2-115 board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects.The following hardware is provided on the DE2-115 board:
In addition to these hardware features, the DE2-115 board has software support for standard I/O interfaces and a control panel facility for accessing various components. Also, the software is provided for supporting a number of demonstrations that illustrate the advanced capabilities of the DE2-115 board. In order to use the DE2-115 board, the user has to be familiar with the Quartus II software. The necessary knowledge can be acquired by reading the tutorials “Getting Started with Altera’s DE2-115 Board” (tut_initialDE2-115.pdf) and “Quartus II Introduction” (which exists in three versions based on the design entry method used, namely Verilog, VHDL or schematic entry). These tutorials are provided in the directory DE2_115_tutorials on the DE2-115 System CD that accompanies the DE2-115 kit and can also be found on Terasic’s DE2-115 web pages.
Block Diagram of the DE2-115 Board
This figure gives the block diagram of the DE2-115 board. To provide maximum flexibility for the user, all connections are made through the Cyclone IV E FPGA device. Thus, the user can configure the FPGA to implement any system design.
PGA device
FPGA configuration
Memory devices
SD Card socket
Connectors
Clock
Audio
Display
Switches and indicators
Other features
Power
LCD Module
The LCD module has built-in
fonts and can be used to display text by sending appropriate commands to the
display controller called HD44780. Detailed information for using the display
is available in its datasheet, which can be found on the manufacturer’s website,
and from the DE2_115_datasheets\LCD folder on the DE2-115 System CD.
A schematic diagram of the
LCD module showing connections to the Cyclone IV E FPGA is given in figure
below. The associated pin assignments appear in Table 1.
Figure 8 Connections
between the LCD module and Cyclone IV E FPGA
Powering-up
the DE2-115 Board
The DE2-115 board comes
with a preloaded configuration bit stream to demonstrate some features of the
board. This bit stream also allows users to see quickly if the board is working
properly. To power-up the board perform the following steps:
1.
Connect the provided USB cable from the host
computer to the USB Blaster connector on the DE2-115 board. For communication
between the host and the DE2-115 board, it is necessary to install the Altera
USB Blaster driver software. If this driver is not already installed on the
host computer, it can be installed as explained in the tutorial “Getting
Started with Altera's DE2-115 Board ”
(tut_initialDE2-115.pdf). This tutorial is available in the directory
DE2_115_tutorials on the DE2-115 System CD.
2.
Turn off the power by pressing the red ON/OFF
switch before connecting the 12V adapter to the DE2-115 board.
3.
Connect a VGA monitor to the VGA port on the
DE2-115 board.
4.
Connect your headset to the line-out audio port
on the DE2-115 board.
5.
Turn the RUN/PROG switch (SW19) on the left edge
of the DE2-115 board to RUN position; the PROG position is used only for the AS
Mode programming.
6.
Recycle the power by turning the red power
switch on the DE2-115 board OFF and ON again .
At this point you should observe the
following:
•
All user LEDs are flashing
•
All 7-segment displays are cycling through the
numbers 0 to F
•
The LCD display shows “Welcome to the Altera
DE2-115”
•
The VGA monitor displays the image shown in
Figure 2-4
•
Set the slide switch SW17 to the DOWN position;
you should hear a 1-kHz sound. Be careful of the very loud volume for avoiding
any discomfort
•
Set the slide switch SW17 to the UP position and
connect the output of an audio player to the line-in connector on the DE2-115
board; on your speaker or headset you should hear the music played from the
audio player (MP3, PC, iPod, or the like)
•
You can also connect a microphone to the
microphone-in connector on the DE2-115 board; your voice will be mixed with the
music playing on the audio player
Configuring
the Cyclone IV E FPGA
The procedure for
downloading a circuit from a host computer to the DE2-115 board is described in
the tutorial Quartus II Introduction. This tutorial
is found in the DE2_115_tutorials folder on the DE2-115 System CD. The user is
encouraged to read the tutorial first, and treat the information below as a
short reference.
The DE2-115 board contains
a serial configuration device that stores configuration data for the Cyclone IV
E FPGA. This configuration data is automatically loaded from the configuration
device into the FPGA every time while power is applied to the board. Using the Quartus II software, it is possible to reconfigure the FPGA
at any time, and it is also possible to change the non-volatile data that is
stored in the serial configuration device. Both types of programming methods
are described below.
1.
JTAG programming: In this method of programming,
named after the IEEE standards Joint Test Action Group, the configuration bit
stream is downloaded directly into the Cyclone IV E FPGA. The FPGA will retain
this configuration as long as power is applied to the board; the configuration
information will be lost when the power is turned off.
2.
AS programming: In this method, called Active
Serial programming, the configuration bit stream is downloaded into the Altera
EPCS64 serial configuration device. It provides non-volatile storage of the bit
stream, so that the information is retained even when the power supply to the
DE2-115 board is turned off. When the board’s power is turned on, the
configuration data in the EPCS64 device is automatically loaded into the
Cyclone IV E FPGA.
Signal
Name
FPGA
Pin No.
Description
I/O
Standard
LCD_DATA[7]
PIN_M5
LCD
Data[7]
3.3V
LCD_DATA[6]
PIN_M3
LCD
Data[6]
3.3V
LCD_DATA[5]
PIN_K2
LCD
Data[5]
3.3V
LCD_DATA[4]
PIN_K1
LCD
Data[4]
3.3V
LCD_DATA[3]
PIN_K7
LCD
Data[3]
3.3V
LCD_DATA[2]
PIN_L2
LCD
Data[2]
3.3V
LCD_DATA[1]
PIN_L1
LCD
Data[1]
3.3V
LCD_DATA[0]
PIN_L3
LCD
Data[0]
3.3V
LCD_EN
PIN_L4
LCD
Enable
3.3V
LCD_RW
PIN_M1
LCD
Read/Write Select, 0 = Write, 1 = Read
3.3V
LCD_RS
PIN_M2
LCD
Command/Data Select, 0 = Command, 1 = Data
3.3V
LCD_ON
PIN_L5
LCD
Power ON/OFF
3.3V
LCD_BLON
PIN_L6
LCD
Back Light ON/OFF
3.3V
Table 1 Pin Assignment
for LCD Module
VEEK-MT
Figure 9 Block Diagram
of VEEK-MT Kit
The video and embedded
evaluation kit with multi touch capability (VEEK-MT) is a product of Terasic. It is an Altera DE2-115 Development and Education Board
with a 7 inch touch screen, ambient light sensor and CMOS digital image sensor.
This kit is suitable for applications such as mobile video, data access, high
quality images and voice applications. Its offers advantages in terms of lower
power consumption, lower cost, and abundance of logic, memory and digital
signal processing capabilities.
The Veek
MT DE-115 FPGA board incorporates a capacitive LCD touch screen. The
touchscreen made up of thin film transistor liquid crystal display. It has LED
backlight. It has a parallel RGB interface.
Figure 10 Top View of
Touch-screen
The touch controller translates x,y coordinates of touch point
into digital data. The diagonal length of the touch screen is 7 inches. Its
resolution is 800x 3 RGB x 480. Its color arrangement is RGB-stripe. It is
glare surface treatment. It has a dot pitch of 0.1926 in height and 0.1790 in
width. It has an active area of 154.08 in height and 85.92 in width.
LCD
Touch Panel Sub-System
The block diagram below
shows the LCD Touch Panel Sub-System
which displays the
contents of the
SDRAM on the LCD Touch Panel. It is also responsible for
the touch detection on the panel. This sub-system consists of two parts, the
LCD Touch Panel and the LCD controllers.
Figure 11 LCD Touch
Panel Subsystem
The LCD Touch Panel which
has been chosen in this system is the TRDB_LTM by Terasic . Through the LCD
Timing Controller the 24-bit display data stored in the SDRAM are displayed on
the LCD Touch Panel. The values of the control registers of the LCD Touch Panel
which are related to its functions are determined by the LCD SPI Controller.
Every time a touch is
detected at any spot of the LCD Touch Panel, it reads and sends out the
corresponding analog coordinates. An analog to digital converter (ADC) transforms
the analog coordinates into the corresponding digital data which are sent to
the FPGA through the second 40-pin expansion header of DE2-115.
It is worth noting that
because of the limited number of I/Os of the
expansion header, the LCD Touch Panel and the ADC share the same clock and chip
enable signals. Consequently, during the design of the LCD SPI Controller there
should be more attention given to the control of these signals in order to
avoid the simultaneous use of the serial port interface by both the LCD Touch
Panel and the ADC.
Finally, it should be noted
that the resolution of the LCD Touch Panel is 800Hx480V. Because the image that
captured from the Camera Sub-system has resolution 640Hx480V, two black bars
are created in the sides of the LCD Touch Panel. In these bars the LCD Timing
Controller draws the four buttons for the Camera control.
LCD Touch Panel Controllers
The following LCD Touch
Panel Controllers which are responsible for the control of the LCD Touch Panel
and the data transfer from DE2-115’s SDRAM, were designed in Verilog HDL [9,
10]:
•
ADC SPI Controller
•
Touch Point Detector Controller
•
LCD Timing Controller
LCD SPI Controller
The ADC SPI controller
receives the digital signals from the LCD Touch Panel’s ADC every time an area
on the Panel is activated through touching. Then, it exports two 12-bit numbers
which represent the x and y coordinates of the area that has been activated.
The Touch Point Detector
Controller receives the coordinates of the activated areas and sends them to
the 7Segment displays of the DE2 in order to be displayed. It also controls if
the x and y coordinates reflect a point in one of the predefined active area.
Camera
Interface
The Camera Sub-System which
is presented in block diagram in the below figure, captures the image from the
sensor, transforms it into RGB format and stores it in the SDRAM of DE2. The
Camera Sub-System has two parts, the TRDB-D5M Camera and the Camera
Controllers.
Figure 12 Camera
Interface Block Diagram
Image Sensor
The Veek
MT DE-115 FPGA board has a 5 megapixel CMOS digital image sensor. The sensor
has good low light performance. During reset, all rows expose at the same time.
It has bulb exposure mode. It is capable of capturing frames on demand. It can
do a vertical and horizontal mirror image. It uses a two wire serial interface.
It is capable of improving image quality when resizing. It is possible to
reduce image size without reducing field of view. There is programmable
controls for gain, frame size, exposure and frame rate parameters. The sensor
requires 3.3V power supply. The maximum signal to noise ratio is 38.1dB. The
sensor has 70.1dB pixel dynamic range. It has a pixel size of 2.2um by 2.2um.
It uses RGB Bayer pattern color filter array. It has a global reset release
shutter type. Its maximum data rate is 96Mps at 96MHz master clock. The sensor
has a 12 bit analog digital conversion resolution. During VGA mode, the sensor
frame rate can be up to 70fps. During full resolution mode, the sensor frame
rate can be up to 15fps.
Ambient Light Sensor
The Veek
MT DE-115 FPGA board includes an ambient light sensor. It is next to the CMOS
digital image sensor. It is used to estimate human-eye response. It allows
accurate luminance measurement in various lighting conditions. It has a
programmable interrupt function with adjustable lower and upper threshold.
Analog gain and integration time can be programmed.
Terasic Video
Image Processing (VIP core)
The Terasic
Multi-Touch IP was obtained from the cd accompanying the Veek-MT
module. The file is needed to use the multi-touch panel in the project. The
frame reader function is used to read video from external memory and to output
it as a stream. Switch function lets video stream switching in real time. Color
space converter function changes image data between color spaces. Control
synchronizer function alters the video stream in real time between two
functions. 2D FIR filter function is a filter that smoothens images. Chroma re-sampler
function alters the sample rate of chroma data.
Clocked video input/output function changes BT-656 video format to Avalon ST
video format and vice versa. Alpha blending mixer function mix and blends
multiple image streams. Deinterlacer function uses
motion adaptive deinterlacing algorithm to change
interlaced video formats to progressive video format. Scaler
II function performs custom scaling and real time
Figure 13 Block diagram
for VIP core
DE2-115 Control Panel
The DE2-115 board comes
with a Control Panel facility that allows users to access various components on
the board from a host computer. The host computer communicates with the board
through a USB connection. The facility can be used to verify the functionality
of components on the board or be used as a debug tool while developing RTL code.
This section first presents some basic functions of the Control Panel, then
describes its structure in block diagram form, and finally describes its
capabilities.
Control
Panel Setup
The Control Panel Software
Utility is located in the directory
“DE2_115_tools/DE2_115_control_panel” in the
DE2-115 System CD. It's free of installation, just copy the whole folder to
your host computer and launch the control panel by executing the
“DE2_115_ControlPanel.exe”. (Windows 7 64-bit Users: If an error message that
shows a missing jtag_client.dll file (cannot find jtag_client.dll) while the
Control Panel is commencing, users should re-launch the DE4_ControlPanel.exe
from the following directory
(/DE2_115_tools/DE2_115_control_panel/win7_64bits))
Specific control circuit should be downloaded to
your FPGA board before the control panel can request it to perform required
tasks. The program will call Quartus II tools to
download the control circuit to the FPGA board through USB-Blaster [USB-0]
connection.
To activate the Control Panel, perform the
following steps:
1.
Make sure Quartus II
10.0 or later version is installed successfully on your PC.
2.
Set the RUN/PROG switch to the RUN position.
3.
Connect the supplied USB cable to the USB
Blaster port, connect the 12V power supply, and turn the power switch ON.
4.
Start the executable DE2_115_ControlPanel.exe on
the host computer. The Control Panel user interface shown in Figure 3-1 will
appear.
5.
The DE2_115_ControlPanel.sof bit stream is
loaded automatically as soon as the DE2_115_control_panel.exe is launched.
6.
In case the connection is disconnected, click on
CONNECT where the .sof will be re-loaded onto the
board.
7.
Note, the Control Panel will occupy the USB port
until you close that port; you cannot use Quartus II
to download a configuration file into the FPGA until the USB port is closed.
8.
The Control Panel is now ready for use;
experience it by setting the ON/OFF status for some LEDs and observing the
result on the DE2-115 board.
Figure 14 The DE2-115
Control Panel
The concept of the DE2-115
Control Panel is illustrated in the above figure. The “Control Circuit” that
performs the control functions is implemented in the FPGA board. It
communicates with the Control Panel window, which is active on the host
computer, via the USB Blaster link. The graphical interface is used to issue
commands to the control circuit. It handles all requests and performs data
transfers between the computer and the DE2-115 board.
Figure 15 The DE2-115
Control Panel concept
The DE2-115 Control Panel
can be used to light up LEDs, change the values displayed on 7-segment and LCD
displays, monitor buttons/switches status, read/write the SDRAM, SRAM, EEPROM
and Flash Memory, monitor the status of an USB device, communicate with the
PS/2 mouse, output VGA color pattern to VGA monitor, verify functionality of
HSMC connector I/Os, communicate with PC via RS-232
interface and read SD Card specification information. The feature of
reading/writing a word or an entire file from/to the Flash Memory allows the
user to develop multimedia applications (Flash Audio Player, Flash Picture
Viewer) without worrying about how to build a Memory Programmer.
Overall
Structure of the DE2-115 Control Panel
The DE2-115 Control Panel is based on a Nios II SOPC system instantiated in the Cyclone IV E FPGA
with software running on the on-chip memory. The software part is implemented
in C code; the hardware part is implemented in Verilog HDL code with SOPC
builder. The source code is not available on the DE2_115 System CD.
To run the Control Panel, users should make the
configuration according to Section Figure below depicts the structure of the
Control Panel. Each input/output device is controlled
by the Nios II Processor instantiated in the FPGA
chip. The communication with the PC is done via the USB Blaster link. The Nios II interprets the commands sent from the PC and
performs the corresponding actions.
Figure 16 block diagram
of the DE2-115 control panel
Controlling
the LEDs, 7-segment Displays and LCD Display
A simple function of the
Control Panel is to allow setting the values displayed on LEDs, 7-segment
displays, and the LCD character display.
Choosing the LED tab leads to the window in the
below figure. Here, you can directly turn the LEDs on or off individually or by
clicking “Light All” or “Unlight
All”.
Figure 17 Controlling
LEDs
Choosing the 7-SEG tab
leads to the window shown in the figure below. From the window, directly use
the left-right arrows to control the 7-SEG patterns on the DE2-115 board which
are updated immediately. Note that the dots of the 7-SEGs are not enabled on
DE2-115 board.
Figure 18 Controlling
7-SEG display
Choosing the LCD tab leads to the window in the
figure below. Text can be written to the LCD display by typing it in the LCD
box then pressing the Set button.
Figure 19 Controlling
the LCD display
The ability to set
arbitrary values into simple display devices is not needed in typical design
activities. However, it gives the user a simple mechanism for verifying that
these devices are functioning correctly in case a malfunction is suspected.
Thus, it can be used for troubleshooting purposes.
Switches
and Push-buttons
Choosing the Switches tab
leads to the window in the figure below. The function is designed to monitor
the status of slide switches and push-buttons in real time and show the status in
a graphical user interface. It can be used to verify the functionality of the
slide switches and push-buttons.
Figure 20 Monitoring
switches and buttons
The ability to check the
status of push-button and slide switch is not needed in typical design
activities. However, it provides users a simple mechanism for verifying if the
buttons and switches are functioning correctly. Thus, it can be used for
troubleshooting purposes.
The DE2-115 board provides
four push-button switches as shown in figure below. Each of these switches is debounced using a Schmitt Trigger circuit, as indicated in
figure below. The four outputs called KEY0, KEY1, KEY2, and KEY3 of the Schmitt
Trigger devices are connected directly to the Cyclone IV E FPGA. Each
push-button switch provides a high logic level when it is not pressed, and
provides a low logic level when depressed. Since the push-button switches are debounced, they are appropriate for using as clock or reset
inputs in a circuit.
Figure 21 Connections
between the push-button and Cyclone IV E FPGA
Figure 22 Push Button Debouncing
There are also 18 slide
switches on the DE2-115 board. These switches are not debounced,
and are assumed for use as level-sensitive data inputs to a circuit. Each
switch is connected directly to a pin on the Cyclone IV E FPGA. When the switch
is in the DOWN position (closest to the edge of the board), it provides a low
logic level to the FPGA, and when the switch is in the UP position it provides
a high logic level.
Figure 23 Connections
between the slide switches and Cyclone IV E FPGA
LEDs
There are 27
user-controllable LEDs on the DE2-115 board. Eighteen red LEDs are situated
above the 18 Slide switches, and eight green LEDs are found above the
push-button switches (the 9th green LED is in the middle of the 7-segment
displays). Each LED is driven directly by a pin on the Cyclone IV E FPGA;
driving its associated pin to a high logic level turns the LED on, and driving
the pin low turns it off. Figure Below shows the connections between LEDs and
Cyclone IV E FPGA.
Figure 24 Connections
between the LEDs and Cyclone IV E FPGA
A list of the pin names on
the Cyclone IV E FPGA that are connected to the slide switches is given in
Table 4-1. Similarly, the pins used to connect to the push-button switches and
LEDs are displayed in Table 2 and Table 3, respectively.
Signal
Name
FPGA
Pin No.
Description
I/O
Standard
SW[0]
PIN_AB28
Slide
Switch[0]
Depending
on JP7
SW[1]
PIN_AC28
Slide
Switch[1]
Depending
on JP7
SW[2]
PIN_AC27
Slide
Switch[2]
Depending
on JP7
SW[3]
PIN_AD27
Slide
Switch[3]
Depending
on JP7
SW[4]
PIN_AB27
Slide
Switch[4]
Depending
on JP7
SW[5]
PIN_AC26
Slide
Switch[5]
Depending
on JP7
SW[6]
PIN_AD26
Slide
Switch[6]
Depending
on JP7
SW[7]
PIN_AB26
Slide
Switch[7]
Depending
on JP7
SW[8]
PIN_AC25
Slide
Switch[8]
Depending
on JP7
SW[9]
PIN_AB25
Slide
Switch[9]
Depending
on JP7
SW[10]
PIN_AC24
Slide
Switch[10]
Depending
on JP7
SW[11]
PIN_AB24
Slide
Switch[11]
Depending
on JP7
SW[12]
PIN_AB23
Slide
Switch[12]
Depending
on JP7
SW[13]
PIN_AA24
Slide
Switch[13]
Depending
on JP7
SW[14]
PIN_AA23
Slide
Switch[14]
Depending
on JP7
SW[15]
PIN_AA22
Slide
Switch[15]
Depending
on JP7
SW[16]
PIN_Y24
Slide
Switch[16]
Depending
on JP7
SW[17]
PIN_Y23
Slide
Switch[17]
Depending
on JP7
Table 2 Pin
Assignments for Slide Switches
Signal
Name
FPGA
Pin No.
Description
I/O
Standard
KEY[0]
PIN_M23
Push-button[0]
Depending
on JP7
KEY[1]
PIN_M21
Push-button[1]
Depending
on JP7
KEY[2]
PIN_N21
Push-button[2]
Depending
on JP7
KEY[3]
PIN_R24
Push-button[3]
Depending
on JP7
Table 3 Pin
Assignments for Push-buttons
Signal
Name
FPGA
Pin No.
Description
I/O
Standard
LEDR[0]
PIN_G19
LED
Red[0]
2.5V
LEDR[1]
PIN_F19
LED
Red[1]
2.5V
LEDR[2]
PIN_E19
LED
Red[2]
2.5V
LEDR[3]
PIN_F21
LED
Red[3]
2.5V
LEDR[4]
PIN_F18
LED
Red[4]
2.5V
LEDR[5]
PIN_E18
LED
Red[5]
2.5V
LEDR[6]
PIN_J19
LED
Red[6]
2.5V
LEDR[7]
PIN_H19
LED
Red[7]
2.5V
LEDR[8]
PIN_J17
LED
Red[8]
2.5V
LEDR[9]
PIN_G17
LED
Red[9]
2.5V
LEDR[10]
PIN_J15
LED
Red[10]
2.5V
LEDR[11]
PIN_H16
LED
Red[11]
2.5V
LEDR[12]
PIN_J16
LED
Red[12]
2.5V
LEDR[13]
PIN_H17
LED
Red[13]
2.5V
LEDR[14]
PIN_F15
LED
Red[14]
2.5V
LEDR[15]
PIN_G15
LED
Red[15]
2.5V
LEDR[16]
PIN_G16
LED
Red[16]
2.5V
LEDR[17]
PIN_H15
LED
Red[17]
2.5V
LEDG[0]
PIN_E21
LED
Green[0]
2.5V
LEDG[1]
PIN_E22
LED
Green[1]
2.5V
LEDG[2]
PIN_E25
LED
Green[2]
2.5V
LEDG[3]
PIN_E24
LED
Green[3]
2.5V
LEDG[4]
PIN_H21
LED
Green[4]
2.5V
LEDG[5]
PIN_G20
LED
Green[5]
2.5V
LEDG[6]
PIN_G22
LED
Green[6]
2.5V
LEDG[7]
PIN_G21
LED
Green[7]
2.5V
LEDG[8]
PIN_F17
LED
Green[8]
2.5V
Table 4 Pin
Assignments for LEDs
7-segment
Displays
The DE2-115 Board has eight
7-segment displays. These displays are arranged into two pairs and a group of
four, behaving the intent of displaying numbers of various sizes. As indicated
in the schematic, the seven segments (common anode) are connected to pins on
Cyclone IV E FPGA. Applying a low logic level to a segment will light it up and
applying a high logic level turns it off.
Each segment in a display is identified by an
index from 0 to 6, with the positions given in Figure 25. Table 5 shows the
assignments of FPGA pins to the 7-segment displays.
Figure 25 Connections
between the 7-segment display HEX0 and Cyclone IV E FPGA
Signal
Name
FPGA
Pin No.
Description
I/O
Standard
HEX0[0]
PIN_G18
Seven
Segment Digit 0[0]
2.5V
HEX0[1]
PIN_F22
Seven
Segment Digit 0[1]
2.5V
HEX0[2]
PIN_E17
Seven
Segment Digit 0[2]
2.5V
HEX0[3]
PIN_L26
Seven
Segment Digit 0[3]
Depending
on JP7
HEX0[4]
PIN_L25
Seven
Segment Digit 0[4]
Depending
on JP7
HEX0[5]
PIN_J22
Seven
Segment Digit 0[5]
Depending
on JP7
HEX0[6]
PIN_H22
Seven
Segment Digit 0[6]
Depending
on JP7
HEX1[0]
PIN_M24
Seven
Segment Digit 1[0]
Depending
on JP7
HEX1[1]
PIN_Y22
Seven
Segment Digit 1[1]
Depending
on JP7
HEX1[2]
PIN_W21
Seven
Segment Digit 1[2]
Depending
on JP7
HEX1[3]
PIN_W22
Seven
Segment Digit 1[3]
Depending
on JP7
HEX1[4]
PIN_W25
Seven
Segment Digit 1[4]
Depending
on JP7
HEX1[5]
PIN_U23
Seven
Segment Digit 1[5]
Depending
on JP7
HEX1[6]
PIN_U24
Seven
Segment Digit 1[6]
Depending
on JP7
HEX2[0]
PIN_AA25
Seven
Segment Digit 2[0]
Depending
on JP7
HEX2[1]
PIN_AA26
Seven
Segment Digit 2[1]
Depending
on JP7
HEX2[2]
PIN_Y25
Seven
Segment Digit 2[2]
Depending
on JP7
HEX2[3]
PIN_W26
Seven
Segment Digit 2[3]
Depending
on JP7
HEX2[4]
PIN_Y26
Seven
Segment Digit 2[4]
Depending
on JP7
HEX2[5]
PIN_W27
Seven
Segment Digit 2[5]
Depending
on JP7
HEX2[6]
PIN_W28
Seven
Segment Digit 2[6]
Depending
on JP7
HEX3[0]
PIN_V21
Seven
Segment Digit 3[0]
Depending
on JP7
HEX3[1]
PIN_U21
Seven
Segment Digit 3[1]
Depending
on JP7
HEX3[2]
PIN_AB20
Seven
Segment Digit 3[2]
Depending
on JP6
HEX3[3]
PIN_AA21
Seven
Segment Digit 3[3]
Depending
on JP6
HEX3[4]
PIN_AD24
Seven
Segment Digit 3[4]
Depending
on JP6
HEX3[5]
PIN_AF23
Seven
Segment Digit 3[5]
Depending
on JP6
HEX3[6]
PIN_Y19
Seven
Segment Digit 3[6]
Depending
on JP6
HEX4[0]
PIN_AB19
Seven
Segment Digit 4[0]
Depending
on JP6
HEX4[1]
PIN_AA19
Seven
Segment Digit 4[1]
Depending
on JP6
HEX4[2]
PIN_AG21
Seven
Segment Digit 4[2]
Depending
on JP6
HEX4[3]
PIN_AH21
Seven
Segment Digit 4[3]
Depending
on JP6
HEX4[4]
PIN_AE19
Seven
Segment Digit 4[4]
Depending
on JP6
HEX4[5]
PIN_AF19
Seven
Segment Digit 4[5]
Depending
on JP6
HEX4[6]
PIN_AE18
Seven
Segment Digit 4[6]
Depending
on JP6
HEX5[0]
PIN_AD18
Seven
Segment Digit 5[0]
Depending
on JP6
HEX5[1]
PIN_AC18
Seven
Segment Digit 5[1]
Depending
on JP6
HEX5[2]
PIN_AB18
Seven
Segment Digit 5[2]
Depending
on JP6
HEX5[3]
PIN_AH19
Seven
Segment Digit 5[3]
Depending
on JP6
HEX5[4]
PIN_AG19
Seven
Segment Digit 5[4]
Depending
on JP6
HEX5[5]
PIN_AF18
Seven
Segment Digit 5[5]
Depending
on JP6
HEX5[6]
PIN_AH18
Seven
Segment Digit 5[6]
Depending
on JP6
HEX6[0]
PIN_AA17
Seven
Segment Digit 6[0]
Depending
on JP6
HEX6[1]
PIN_AB16
Seven
Segment Digit 6[1]
Depending
on JP6
HEX6[2]
PIN_AA16
Seven
Segment Digit 6[2]
Depending
on JP6
HEX6[3]
PIN_AB17
Seven
Segment Digit 6[3]
Depending
on JP6
HEX6[4]
PIN_AB15
Seven
Segment Digit 6[4]
Depending
on JP6
HEX6[5]
PIN_AA15
Seven
Segment Digit 6[5]
Depending
on JP6
HEX6[6]
PIN_AC17
Seven
Segment Digit 6[6]
Depending
on JP6
HEX7[0]
PIN_AD17
Seven
Segment Digit 7[0]
Depending
on JP6
HEX7[1]
PIN_AE17
Seven
Segment Digit 7[1]
Depending
on JP6
HEX7[2]
PIN_AG17
Seven
Segment Digit 7[2]
Depending
on JP6
HEX7[3]
PIN_AH17
Seven
Segment Digit 7[3]
Depending
on JP6
HEX7[4]
PIN_AF17
Seven
Segment Digit 7[4]
Depending
on JP6
HEX7[5]
PIN_AG18
Seven
Segment Digit 7[5]
Depending
on JP6
HEX7[6]
PIN_AA14
Seven
Segment Digit 7[6]
3.3V
Table 5 Pin
Assignments for 7-segment Displays
Memory
Controller and Programmer
The Control Panel can be
used to write/read data to/from the SDRAM, SRAM, EEPROM, and Flash chips on the
DE2-115 board. As an example, we will describe how the SDRAM may be accessed;
the same approach is used to access the SRAM, EEPROM, and Flash. Click on the
Memory tab and select “SDRAM” to reach the window in the figure below.
Figure 26 Accessing the
SDRAM
A 16-bit word can be
written into the SDRAM by entering the address of the desired location,
specifying the data to be written, and pressing the Write button. Contents of
the location can be read by pressing the Read button. Above figure depicts the
result of writing the hexadecimal value 06CA into offset address 200, followed
by reading the same location.
The Sequential Write
function of the Control Panel is used to write the contents of a file into the
SDRAM as follows:
1.
Specify the starting address in the Address box.
2.
Specify the number of bytes to be written in the
Length box. If the entire file is to be loaded, then a checkmark may be placed
in the File Length box instead of giving the number of bytes.
3.
To initiate the writing process, click on the Write
a File to Memory button.
4.
When the Control Panel responds with the
standard Windows dialog box asking for the source file, specify the desired
file in the usual manner.
The Control Panel also
supports loading files with a .hex extension. Files with a .hex extension are
ASCII text files that specify memory values using ASCII characters to represent
hexadecimal values. For example, a file containing the line
0123456789ABCDEF
Defines eight 8-bit values: 01, 23, 45, 67, 89,
AB, CD, EF. These values will be loaded consecutively
into the memory.
The Sequential Read
function is used to read the contents of the SDRAM and fill them into a file as
follows:
1.
Specify the starting address in the Address box.
2.
Specify the number of bytes to be copied into
the file in the Length box. If the entire contents of the SDRAM are to be
copied (which involves all 128 Mbytes), then place a checkmark in the Entire
Memory box.
3.
Press Load Memory Content to a File button.
4.
When the Control Panel responds with the
standard Windows dialog box asking for the destination file, specify the
desired file in the usual manner.
Users can use the similar way to access the SRAM, EEPROM and
Flash. Please note that users need to erase the Flash before writing data to
it.
USB
Monitoring
The Control Panel provides
users a USB monitoring tool which monitors the status of the USB devices
connected to the USB port on the DE2-115 board. By plugging in a USB device to
the USB host port of the board, the device type is displayed on the control
window. Below Figure shows a USB mouse plugged into the host USB port.
Figure 27 USB Mouse
Monitoring Tool
PS/2
Device
The Control Panel provides
users a PS/2 monitoring tool which monitors the real-time status of a PS/2
mouse connected to the DE2-115 board. The movement of the mouse and the status
of the three buttons will be shown in the graphical and text interface. The
mouse movement is translated as a position (x,y) with range from (0,0)~(1023,767). This function
can be used to verify the functionality of the PS/2 connection.
Follow the steps below to exercise the PS/2
Mouse Monitoring tool:
1.
Choosing the PS/2 tab leads to the window in the
Figure Below.
2.
Plug a PS/2 mouse to the PS/2 port on the
DE2-115 board.
3.
Press the Start button to start the PS/2 mouse
monitoring process, and the button caption is changed from Start to Stop. In
the monitoring process, the status of the PS/2 mouse is updated and shown in
the Control Panel’s GUI window in real-time. Press Stop to terminate the
monitoring process.
Figure 28 PS/2 Mouse
Monitoring Tool
SD
Card
The function is designed to
read the identification and specification information of the SD Card. The 4-bit
SD MODE is used to access the SD Card. This function can be used to verify the
functionality of the SD Card Interface. Follow the steps below to exercise the
SD Card:
1.
Choosing the SD Card tab leads to the window in
the figure below.
2.
Insert an SD Card to the DE2-115 board, and then
press the Read button to read the SD Card. The SD Card’s identification,
specification, and file format information will be displayed in the control
window.
Figure 29 Reading the SD
Card Identification and Specification
VGA
DE2-115 Control Panel
provides VGA pattern function that allows users to output color pattern to
LCD/CRT monitor using the DE2-115 board. Follow the steps below to generate the
VGA pattern function:
1.
Choosing the VGA tab leads to the window in the
figure below.
2.
Plug a D-sub cable to VGA connector of the
DE2-115 board and LCD/CRT monitor.
3.
The LCD/CRT monitor will display the same color
pattern on the control panel window.
4.
Click the drop down menu shown in the figure
below where you can output the selected color individually.
Figure 30 Controlling
VGA display
HSMC
Select the HSMC tab to
reach the window shown in the figure below. This function is designed to verify
the functionality of the signals located on the HSMC connector. Before running
the HSMC loopback verification test, follow the instruction noted under the
Loopback Installation section and click on Verify. Please note to turn off the
DE2-115 board before the HSMC loopback adapter is installed to prevent any
damage to the board.
Figure 31 HSMC loopback
verification test performed under Control Panel
RS-232
Communication
The Control Panel allows
users to verify the operation of the RS-232 serial communication interface on
the DE2-115. The setup is established by connecting a RS-232 9-pin male to
female cable from the PC to the RS-232 port where the Control Panel communicates
to the terminal emulator software on the PC, or vice versa. Alternatively, a
RS-232 loopback cable can also be used if you do not wish to use the PC to
verify the test. The Receive terminal window on the Control Panel monitors the
serial communication status. Follow the steps below to initiate the RS-232
communication:
1.
Choosing the RS-232 tab leads to the window in
the figure below.
2.
Plug in a RS-232 9-pin male to female cable from
PC to RS-232 port or a RS-232 loopback cable directly to RS-232 port.
3.
The RS-232 settings are provided below in case a
connection from the PC is used:
•
Baud Rate: 115200
•
Parity Check Bit: None
•
Data Bits: 8
•
Stop Bits: 1
•
Flow Control (CTS/RTS): ON
4.
To begin the communication, enter specific
letters followed by clicking Send. During the communication process, observe
the status of the Receive terminal window to verify its operation.
Figure 32 RS-232 Serial
Communication
Nios
II Processor
Nios II is a soft-core processor targeted for
Altera’s FPGA devices. As opposed to a fixed prefabricated processor, this
soft-core processor is described by HDL codes and then mapped onto FPGA’s
generic logic cells. Thus it can be configured and tuned by adding or removing
features to meet performance or cost goals. This approach offers more
flexibility.
There are three basic versions of Nios II in the SOPC Builder :
•
Nios II/f: The fast core is designed for optimal
performance. It has a 6-stage pipeline, instruction cache, data cache, and
dynamic branch prediction.
•
Nios II/s: The standard core is designed for small
size while maintaining good performance. It has a 5-stage pipeline, instruction
cache, and static branch prediction.
•
Nios II/e: The economy core is designed for optimal
size. It is not pipelined and contains no cache.
Figure 33 Nios II Processor Dialog
JTAG
UART Core
The JTAG UART (Universal
Asynchronous Receiver and Transmitter) core with Avalon interface provides a
method to communicate serial character streams between a host PC and the board.
On one side, the Nios II processor communicates with
the core by reading and writing control and data registers. To increase the
performance and regulate data transmission, a write FIFO buffer and a read FIFO
buffer are also included in this core. On the other side, the core uses the
JTAG circuitry built into Altera FPGA and provides host access via the JTAG
pins on the FPGA. The host PC can connect to the FPGA via any Altera JTAG
download cable, such as the USB-Blaster cable.
Figure 34 JTAG UART Core
Block Diagram
The software support for
the JTAG UART core is provided by Altera as well. For the Nios
II processor, device drivers are provided in the HAL (Hardware Abstraction
Layer) system library, allowing software to access the core using the ANSI C
Standard Library functions, such as getchar() and printf(). For the host PC, Altera provides JTAG terminal
software NIOS EDS that manages the connection to the target, decodes the JTAG
data stream, and displays characters on screen. The connection between a host
PC and an Nios II system
containing a JTAG UART core is shown below.
Figure 35 Host-Target
Connection
The JTAG UART core in our Nios II system is used to debug the software program. For
example, print out acceleration data or write image data into a file of the
host PC. In the SOPC Builder, this core is configured in default settings. In
our Nios II system, the size of Nios
II processor is not a problem so Nios II/f is selected
for optimal performance. The configuration dialog is displayed in Figure. In
addition, we also need to specify the memories and locations of the reset
vector and exception vector. A typical system usually adopts a nonvolatile
memory module for the reset code. Thus the Flash memory is selected as the
reset vector memory. Since our software program requires a relatively large
amount of memory, SRAM is adopted as the exception vector memory. The other
settings for our Nios II processor is default. Note
that a level-1 JTAG debug module is used in the default setting.
Communication
JTAG
Chain on DE2-115 Board
To use JTAG interface for
configuring FPGA device, the JTAG chain on DE2-115 must form a close loop that
allows Quartus II programmer to detect FPGA device.
Figure illustrates the JTAG chain on DE2-115 board. Shorting pin1 and pin2 on
JP3 can disable the JTAG signals on HSMC connector that will form a close JTAG
loop chain on DE2-115 board. Thus, only the on board FPGA device (Cyclone IV E)
will be detected by Quartus II programmer. If users
want to include another FPGA device or interface containing FPGA device in the
chain via HSMC connector, short pin2 and pin3 on JP3 to enable the JTAG signal
ports on the HSMC connector.
Figure 36 The JTAG chain
on DE2-115 board
Figure 37 The JTAG chain
configuration header
The sections below describe
the steps used to perform both JTAG and AS programming. For both methods the
DE2-115 board is connected to a host computer via a USB cable. Using this
connection, the board will be identified by the host computer as an Altera USB
Blaster device. The process for installing on the host computer the necessary
software device driver that communicates with the USB Blaster is described in
the tutorial “Getting Started with Altera’s DE2-115 Board” (tut_initialDE2-115.pdf).
This tutorial is available on the DE2-115 System CD.
Configuring the FPGA in JTAG Module
Figure illustrates the JTAG
configuration setup. To download a configuration bit stream into the Cyclone IV
E FPGA, perform the following steps:
•
Ensure that power is applied to the DE2-115
board
•
Configure the JTAG programming circuit by
setting the RUN/PROG slide switch (SW19) to the RUN position Connect the
supplied USB cable to the USB Blaster port on the DE2-115 board
•
The FPGA can now be programmed by using the Quartus II Programmer to select a configuration bit stream
file with the .sof filename extension
Figure 38 The JTAG
configuration scheme
LCD Module
The LCD module has built-in
fonts and can be used to display text by sending appropriate commands to the
display controller called HD44780. Detailed information for using the display
is available in its datasheet, which can be found on the manufacturer’s website,
and from the DE2_115_datasheets\LCD folder on the DE2-115 System CD.
A schematic diagram of the
LCD module showing connections to the Cyclone IV E FPGA is given in figure
below. The associated pin assignments appear in Table 1.
Figure 8 Connections
between the LCD module and Cyclone IV E FPGA
Powering-up
the DE2-115 Board
The DE2-115 board comes
with a preloaded configuration bit stream to demonstrate some features of the
board. This bit stream also allows users to see quickly if the board is working
properly. To power-up the board perform the following steps:
1.
Connect the provided USB cable from the host
computer to the USB Blaster connector on the DE2-115 board. For communication
between the host and the DE2-115 board, it is necessary to install the Altera
USB Blaster driver software. If this driver is not already installed on the
host computer, it can be installed as explained in the tutorial “Getting
Started with Altera's DE2-115 Board ”
(tut_initialDE2-115.pdf). This tutorial is available in the directory
DE2_115_tutorials on the DE2-115 System CD.
2.
Turn off the power by pressing the red ON/OFF
switch before connecting the 12V adapter to the DE2-115 board.
3.
Connect a VGA monitor to the VGA port on the
DE2-115 board.
4.
Connect your headset to the line-out audio port
on the DE2-115 board.
5.
Turn the RUN/PROG switch (SW19) on the left edge
of the DE2-115 board to RUN position; the PROG position is used only for the AS
Mode programming.
6.
Recycle the power by turning the red power
switch on the DE2-115 board OFF and ON again .
At this point you should observe the
following:
•
All user LEDs are flashing
•
All 7-segment displays are cycling through the
numbers 0 to F
•
The LCD display shows “Welcome to the Altera
DE2-115”
•
The VGA monitor displays the image shown in
Figure 2-4
•
Set the slide switch SW17 to the DOWN position;
you should hear a 1-kHz sound. Be careful of the very loud volume for avoiding
any discomfort
•
Set the slide switch SW17 to the UP position and
connect the output of an audio player to the line-in connector on the DE2-115
board; on your speaker or headset you should hear the music played from the
audio player (MP3, PC, iPod, or the like)
•
You can also connect a microphone to the
microphone-in connector on the DE2-115 board; your voice will be mixed with the
music playing on the audio player
Configuring
the Cyclone IV E FPGA
The procedure for
downloading a circuit from a host computer to the DE2-115 board is described in
the tutorial Quartus II Introduction. This tutorial
is found in the DE2_115_tutorials folder on the DE2-115 System CD. The user is
encouraged to read the tutorial first, and treat the information below as a
short reference.
The DE2-115 board contains
a serial configuration device that stores configuration data for the Cyclone IV
E FPGA. This configuration data is automatically loaded from the configuration
device into the FPGA every time while power is applied to the board. Using the Quartus II software, it is possible to reconfigure the FPGA
at any time, and it is also possible to change the non-volatile data that is
stored in the serial configuration device. Both types of programming methods
are described below.
1.
JTAG programming: In this method of programming,
named after the IEEE standards Joint Test Action Group, the configuration bit
stream is downloaded directly into the Cyclone IV E FPGA. The FPGA will retain
this configuration as long as power is applied to the board; the configuration
information will be lost when the power is turned off.
2.
AS programming: In this method, called Active
Serial programming, the configuration bit stream is downloaded into the Altera
EPCS64 serial configuration device. It provides non-volatile storage of the bit
stream, so that the information is retained even when the power supply to the
DE2-115 board is turned off. When the board’s power is turned on, the
configuration data in the EPCS64 device is automatically loaded into the
Cyclone IV E FPGA.
|
Signal
Name |
FPGA
Pin No. |
Description
|
I/O Standard |
|
|
|
|
|
|
LCD_DATA[7]
|
PIN_M5 |
LCD
Data[7] |
3.3V |
|
LCD_DATA[6]
|
PIN_M3 |
LCD
Data[6] |
3.3V |
|
LCD_DATA[5]
|
PIN_K2 |
LCD
Data[5] |
3.3V |
|
LCD_DATA[4]
|
PIN_K1 |
LCD
Data[4] |
3.3V |
|
LCD_DATA[3]
|
PIN_K7 |
LCD
Data[3] |
3.3V |
|
LCD_DATA[2]
|
PIN_L2 |
LCD
Data[2] |
3.3V |
|
LCD_DATA[1]
|
PIN_L1 |
LCD
Data[1] |
3.3V |
|
LCD_DATA[0]
|
PIN_L3 |
LCD
Data[0] |
3.3V |
|
LCD_EN |
PIN_L4 |
LCD
Enable |
3.3V |
|
LCD_RW |
PIN_M1 |
LCD
Read/Write Select, 0 = Write, 1 = Read |
3.3V |
|
LCD_RS |
PIN_M2 |
LCD
Command/Data Select, 0 = Command, 1 = Data |
3.3V |
|
LCD_ON |
PIN_L5 |
LCD
Power ON/OFF |
3.3V |
|
LCD_BLON
|
PIN_L6 |
LCD
Back Light ON/OFF |
3.3V |
Table 1 Pin Assignment
for LCD Module
VEEK-MT
Figure 9 Block Diagram
of VEEK-MT Kit
The video and embedded
evaluation kit with multi touch capability (VEEK-MT) is a product of Terasic. It is an Altera DE2-115 Development and Education Board
with a 7 inch touch screen, ambient light sensor and CMOS digital image sensor.
This kit is suitable for applications such as mobile video, data access, high
quality images and voice applications. Its offers advantages in terms of lower
power consumption, lower cost, and abundance of logic, memory and digital
signal processing capabilities.
The Veek
MT DE-115 FPGA board incorporates a capacitive LCD touch screen. The
touchscreen made up of thin film transistor liquid crystal display. It has LED
backlight. It has a parallel RGB interface.
Figure 10 Top View of
Touch-screen
The touch controller translates x,y coordinates of touch point
into digital data. The diagonal length of the touch screen is 7 inches. Its
resolution is 800x 3 RGB x 480. Its color arrangement is RGB-stripe. It is
glare surface treatment. It has a dot pitch of 0.1926 in height and 0.1790 in
width. It has an active area of 154.08 in height and 85.92 in width.
LCD
Touch Panel Sub-System
The block diagram below
shows the LCD Touch Panel Sub-System
which displays the
contents of the
SDRAM on the LCD Touch Panel. It is also responsible for
the touch detection on the panel. This sub-system consists of two parts, the
LCD Touch Panel and the LCD controllers.
Figure 11 LCD Touch
Panel Subsystem
The LCD Touch Panel which
has been chosen in this system is the TRDB_LTM by Terasic . Through the LCD
Timing Controller the 24-bit display data stored in the SDRAM are displayed on
the LCD Touch Panel. The values of the control registers of the LCD Touch Panel
which are related to its functions are determined by the LCD SPI Controller.
Every time a touch is
detected at any spot of the LCD Touch Panel, it reads and sends out the
corresponding analog coordinates. An analog to digital converter (ADC) transforms
the analog coordinates into the corresponding digital data which are sent to
the FPGA through the second 40-pin expansion header of DE2-115.
It is worth noting that
because of the limited number of I/Os of the
expansion header, the LCD Touch Panel and the ADC share the same clock and chip
enable signals. Consequently, during the design of the LCD SPI Controller there
should be more attention given to the control of these signals in order to
avoid the simultaneous use of the serial port interface by both the LCD Touch
Panel and the ADC.
Finally, it should be noted
that the resolution of the LCD Touch Panel is 800Hx480V. Because the image that
captured from the Camera Sub-system has resolution 640Hx480V, two black bars
are created in the sides of the LCD Touch Panel. In these bars the LCD Timing
Controller draws the four buttons for the Camera control.
LCD Touch Panel Controllers
The following LCD Touch
Panel Controllers which are responsible for the control of the LCD Touch Panel
and the data transfer from DE2-115’s SDRAM, were designed in Verilog HDL [9,
10]:
•
ADC SPI Controller
•
Touch Point Detector Controller
•
LCD Timing Controller
LCD SPI Controller
The ADC SPI controller
receives the digital signals from the LCD Touch Panel’s ADC every time an area
on the Panel is activated through touching. Then, it exports two 12-bit numbers
which represent the x and y coordinates of the area that has been activated.
The Touch Point Detector
Controller receives the coordinates of the activated areas and sends them to
the 7Segment displays of the DE2 in order to be displayed. It also controls if
the x and y coordinates reflect a point in one of the predefined active area.
Camera
Interface
The Camera Sub-System which
is presented in block diagram in the below figure, captures the image from the
sensor, transforms it into RGB format and stores it in the SDRAM of DE2. The
Camera Sub-System has two parts, the TRDB-D5M Camera and the Camera
Controllers.
Figure 12 Camera
Interface Block Diagram
Image Sensor
The Veek
MT DE-115 FPGA board has a 5 megapixel CMOS digital image sensor. The sensor
has good low light performance. During reset, all rows expose at the same time.
It has bulb exposure mode. It is capable of capturing frames on demand. It can
do a vertical and horizontal mirror image. It uses a two wire serial interface.
It is capable of improving image quality when resizing. It is possible to
reduce image size without reducing field of view. There is programmable
controls for gain, frame size, exposure and frame rate parameters. The sensor
requires 3.3V power supply. The maximum signal to noise ratio is 38.1dB. The
sensor has 70.1dB pixel dynamic range. It has a pixel size of 2.2um by 2.2um.
It uses RGB Bayer pattern color filter array. It has a global reset release
shutter type. Its maximum data rate is 96Mps at 96MHz master clock. The sensor
has a 12 bit analog digital conversion resolution. During VGA mode, the sensor
frame rate can be up to 70fps. During full resolution mode, the sensor frame
rate can be up to 15fps.
Ambient Light Sensor
The Veek
MT DE-115 FPGA board includes an ambient light sensor. It is next to the CMOS
digital image sensor. It is used to estimate human-eye response. It allows
accurate luminance measurement in various lighting conditions. It has a
programmable interrupt function with adjustable lower and upper threshold.
Analog gain and integration time can be programmed.
Terasic Video
Image Processing (VIP core)
The Terasic
Multi-Touch IP was obtained from the cd accompanying the Veek-MT
module. The file is needed to use the multi-touch panel in the project. The
frame reader function is used to read video from external memory and to output
it as a stream. Switch function lets video stream switching in real time. Color
space converter function changes image data between color spaces. Control
synchronizer function alters the video stream in real time between two
functions. 2D FIR filter function is a filter that smoothens images. Chroma re-sampler
function alters the sample rate of chroma data.
Clocked video input/output function changes BT-656 video format to Avalon ST
video format and vice versa. Alpha blending mixer function mix and blends
multiple image streams. Deinterlacer function uses
motion adaptive deinterlacing algorithm to change
interlaced video formats to progressive video format. Scaler
II function performs custom scaling and real time
Figure 13 Block diagram
for VIP core
DE2-115 Control Panel
The DE2-115 board comes
with a Control Panel facility that allows users to access various components on
the board from a host computer. The host computer communicates with the board
through a USB connection. The facility can be used to verify the functionality
of components on the board or be used as a debug tool while developing RTL code.
This section first presents some basic functions of the Control Panel, then
describes its structure in block diagram form, and finally describes its
capabilities.
Control
Panel Setup
The Control Panel Software
Utility is located in the directory
“DE2_115_tools/DE2_115_control_panel” in the
DE2-115 System CD. It's free of installation, just copy the whole folder to
your host computer and launch the control panel by executing the
“DE2_115_ControlPanel.exe”. (Windows 7 64-bit Users: If an error message that
shows a missing jtag_client.dll file (cannot find jtag_client.dll) while the
Control Panel is commencing, users should re-launch the DE4_ControlPanel.exe
from the following directory
(/DE2_115_tools/DE2_115_control_panel/win7_64bits))
Specific control circuit should be downloaded to
your FPGA board before the control panel can request it to perform required
tasks. The program will call Quartus II tools to
download the control circuit to the FPGA board through USB-Blaster [USB-0]
connection.
To activate the Control Panel, perform the
following steps:
1.
Make sure Quartus II
10.0 or later version is installed successfully on your PC.
2.
Set the RUN/PROG switch to the RUN position.
3.
Connect the supplied USB cable to the USB
Blaster port, connect the 12V power supply, and turn the power switch ON.
4.
Start the executable DE2_115_ControlPanel.exe on
the host computer. The Control Panel user interface shown in Figure 3-1 will
appear.
5.
The DE2_115_ControlPanel.sof bit stream is
loaded automatically as soon as the DE2_115_control_panel.exe is launched.
6.
In case the connection is disconnected, click on
CONNECT where the .sof will be re-loaded onto the
board.
7.
Note, the Control Panel will occupy the USB port
until you close that port; you cannot use Quartus II
to download a configuration file into the FPGA until the USB port is closed.
8.
The Control Panel is now ready for use;
experience it by setting the ON/OFF status for some LEDs and observing the
result on the DE2-115 board.
Figure 14 The DE2-115
Control Panel
The concept of the DE2-115
Control Panel is illustrated in the above figure. The “Control Circuit” that
performs the control functions is implemented in the FPGA board. It
communicates with the Control Panel window, which is active on the host
computer, via the USB Blaster link. The graphical interface is used to issue
commands to the control circuit. It handles all requests and performs data
transfers between the computer and the DE2-115 board.
Figure 15 The DE2-115
Control Panel concept
The DE2-115 Control Panel
can be used to light up LEDs, change the values displayed on 7-segment and LCD
displays, monitor buttons/switches status, read/write the SDRAM, SRAM, EEPROM
and Flash Memory, monitor the status of an USB device, communicate with the
PS/2 mouse, output VGA color pattern to VGA monitor, verify functionality of
HSMC connector I/Os, communicate with PC via RS-232
interface and read SD Card specification information. The feature of
reading/writing a word or an entire file from/to the Flash Memory allows the
user to develop multimedia applications (Flash Audio Player, Flash Picture
Viewer) without worrying about how to build a Memory Programmer.
Overall
Structure of the DE2-115 Control Panel
The DE2-115 Control Panel is based on a Nios II SOPC system instantiated in the Cyclone IV E FPGA
with software running on the on-chip memory. The software part is implemented
in C code; the hardware part is implemented in Verilog HDL code with SOPC
builder. The source code is not available on the DE2_115 System CD.
To run the Control Panel, users should make the
configuration according to Section Figure below depicts the structure of the
Control Panel. Each input/output device is controlled
by the Nios II Processor instantiated in the FPGA
chip. The communication with the PC is done via the USB Blaster link. The Nios II interprets the commands sent from the PC and
performs the corresponding actions.
Figure 16 block diagram
of the DE2-115 control panel
Controlling
the LEDs, 7-segment Displays and LCD Display
A simple function of the
Control Panel is to allow setting the values displayed on LEDs, 7-segment
displays, and the LCD character display.
Choosing the LED tab leads to the window in the
below figure. Here, you can directly turn the LEDs on or off individually or by
clicking “Light All” or “Unlight
All”.
Figure 17 Controlling
LEDs
Choosing the 7-SEG tab
leads to the window shown in the figure below. From the window, directly use
the left-right arrows to control the 7-SEG patterns on the DE2-115 board which
are updated immediately. Note that the dots of the 7-SEGs are not enabled on
DE2-115 board.
Figure 18 Controlling
7-SEG display
Choosing the LCD tab leads to the window in the
figure below. Text can be written to the LCD display by typing it in the LCD
box then pressing the Set button.
Figure 19 Controlling
the LCD display
The ability to set
arbitrary values into simple display devices is not needed in typical design
activities. However, it gives the user a simple mechanism for verifying that
these devices are functioning correctly in case a malfunction is suspected.
Thus, it can be used for troubleshooting purposes.
Switches
and Push-buttons
Choosing the Switches tab
leads to the window in the figure below. The function is designed to monitor
the status of slide switches and push-buttons in real time and show the status in
a graphical user interface. It can be used to verify the functionality of the
slide switches and push-buttons.
Figure 20 Monitoring
switches and buttons
The ability to check the
status of push-button and slide switch is not needed in typical design
activities. However, it provides users a simple mechanism for verifying if the
buttons and switches are functioning correctly. Thus, it can be used for
troubleshooting purposes.
The DE2-115 board provides
four push-button switches as shown in figure below. Each of these switches is debounced using a Schmitt Trigger circuit, as indicated in
figure below. The four outputs called KEY0, KEY1, KEY2, and KEY3 of the Schmitt
Trigger devices are connected directly to the Cyclone IV E FPGA. Each
push-button switch provides a high logic level when it is not pressed, and
provides a low logic level when depressed. Since the push-button switches are debounced, they are appropriate for using as clock or reset
inputs in a circuit.
Figure 21 Connections
between the push-button and Cyclone IV E FPGA
Figure 22 Push Button Debouncing
There are also 18 slide
switches on the DE2-115 board. These switches are not debounced,
and are assumed for use as level-sensitive data inputs to a circuit. Each
switch is connected directly to a pin on the Cyclone IV E FPGA. When the switch
is in the DOWN position (closest to the edge of the board), it provides a low
logic level to the FPGA, and when the switch is in the UP position it provides
a high logic level.
Figure 23 Connections
between the slide switches and Cyclone IV E FPGA
LEDs
There are 27
user-controllable LEDs on the DE2-115 board. Eighteen red LEDs are situated
above the 18 Slide switches, and eight green LEDs are found above the
push-button switches (the 9th green LED is in the middle of the 7-segment
displays). Each LED is driven directly by a pin on the Cyclone IV E FPGA;
driving its associated pin to a high logic level turns the LED on, and driving
the pin low turns it off. Figure Below shows the connections between LEDs and
Cyclone IV E FPGA.
Figure 24 Connections
between the LEDs and Cyclone IV E FPGA
A list of the pin names on
the Cyclone IV E FPGA that are connected to the slide switches is given in
Table 4-1. Similarly, the pins used to connect to the push-button switches and
LEDs are displayed in Table 2 and Table 3, respectively.
|
Signal
Name |
FPGA
Pin No. |
Description
|
I/O
Standard |
|
SW[0] |
PIN_AB28
|
Slide
Switch[0] |
Depending
on JP7 |
|
SW[1] |
PIN_AC28
|
Slide
Switch[1] |
Depending
on JP7 |
|
SW[2] |
PIN_AC27
|
Slide
Switch[2] |
Depending
on JP7 |
|
SW[3] |
PIN_AD27
|
Slide
Switch[3] |
Depending
on JP7 |
|
SW[4] |
PIN_AB27
|
Slide
Switch[4] |
Depending
on JP7 |
|
SW[5] |
PIN_AC26
|
Slide
Switch[5] |
Depending
on JP7 |
|
SW[6] |
PIN_AD26
|
Slide
Switch[6] |
Depending
on JP7 |
|
SW[7] |
PIN_AB26
|
Slide
Switch[7] |
Depending
on JP7 |
|
SW[8] |
PIN_AC25
|
Slide
Switch[8] |
Depending
on JP7 |
|
SW[9] |
PIN_AB25
|
Slide
Switch[9] |
Depending
on JP7 |
|
SW[10] |
PIN_AC24
|
Slide
Switch[10] |
Depending
on JP7 |
|
SW[11] |
PIN_AB24
|
Slide
Switch[11] |
Depending
on JP7 |
|
SW[12] |
PIN_AB23
|
Slide
Switch[12] |
Depending
on JP7 |
|
SW[13] |
PIN_AA24
|
Slide
Switch[13] |
Depending
on JP7 |
|
SW[14] |
PIN_AA23
|
Slide
Switch[14] |
Depending
on JP7 |
|
SW[15] |
PIN_AA22
|
Slide
Switch[15] |
Depending
on JP7 |
|
SW[16] |
PIN_Y24
|
Slide
Switch[16] |
Depending
on JP7 |
|
SW[17] |
PIN_Y23
|
Slide
Switch[17] |
Depending
on JP7 |
Table 2 Pin
Assignments for Slide Switches
|
Signal
Name |
FPGA
Pin No. |
Description
|
I/O
Standard |
|
KEY[0] |
PIN_M23
|
Push-button[0]
|
Depending
on JP7 |
|
KEY[1] |
PIN_M21
|
Push-button[1]
|
Depending
on JP7 |
|
KEY[2] |
PIN_N21
|
Push-button[2]
|
Depending
on JP7 |
|
KEY[3] |
PIN_R24
|
Push-button[3]
|
Depending
on JP7 |
Table 3 Pin
Assignments for Push-buttons
|
Signal
Name |
FPGA
Pin No. |
Description
|
I/O
Standard |
|
LEDR[0]
|
PIN_G19
|
LED
Red[0] |
2.5V |
|
LEDR[1]
|
PIN_F19
|
LED
Red[1] |
2.5V |
|
LEDR[2]
|
PIN_E19
|
LED
Red[2] |
2.5V |
|
LEDR[3]
|
PIN_F21
|
LED
Red[3] |
2.5V |
|
LEDR[4]
|
PIN_F18
|
LED
Red[4] |
2.5V |
|
LEDR[5]
|
PIN_E18
|
LED
Red[5] |
2.5V |
|
LEDR[6]
|
PIN_J19
|
LED
Red[6] |
2.5V |
|
LEDR[7]
|
PIN_H19
|
LED
Red[7] |
2.5V |
|
LEDR[8]
|
PIN_J17
|
LED
Red[8] |
2.5V |
|
LEDR[9]
|
PIN_G17
|
LED
Red[9] |
2.5V |
|
LEDR[10]
|
PIN_J15
|
LED
Red[10] |
2.5V |
|
LEDR[11]
|
PIN_H16
|
LED
Red[11] |
2.5V |
|
LEDR[12]
|
PIN_J16
|
LED
Red[12] |
2.5V |
|
LEDR[13]
|
PIN_H17
|
LED
Red[13] |
2.5V |
|
LEDR[14]
|
PIN_F15
|
LED
Red[14] |
2.5V |
|
LEDR[15]
|
PIN_G15
|
LED
Red[15] |
2.5V |
|
LEDR[16]
|
PIN_G16
|
LED
Red[16] |
2.5V |
|
LEDR[17]
|
PIN_H15
|
LED
Red[17] |
2.5V |
|
LEDG[0]
|
PIN_E21
|
LED
Green[0] |
2.5V |
|
LEDG[1]
|
PIN_E22
|
LED
Green[1] |
2.5V |
|
LEDG[2]
|
PIN_E25
|
LED
Green[2] |
2.5V |
|
LEDG[3]
|
PIN_E24
|
LED
Green[3] |
2.5V |
|
LEDG[4]
|
PIN_H21
|
LED
Green[4] |
2.5V |
|
LEDG[5]
|
PIN_G20
|
LED
Green[5] |
2.5V |
|
LEDG[6]
|
PIN_G22
|
LED
Green[6] |
2.5V |
|
LEDG[7]
|
PIN_G21
|
LED
Green[7] |
2.5V |
|
LEDG[8]
|
PIN_F17
|
LED
Green[8] |
2.5V |
Table 4 Pin
Assignments for LEDs
7-segment
Displays
The DE2-115 Board has eight
7-segment displays. These displays are arranged into two pairs and a group of
four, behaving the intent of displaying numbers of various sizes. As indicated
in the schematic, the seven segments (common anode) are connected to pins on
Cyclone IV E FPGA. Applying a low logic level to a segment will light it up and
applying a high logic level turns it off.
Each segment in a display is identified by an
index from 0 to 6, with the positions given in Figure 25. Table 5 shows the
assignments of FPGA pins to the 7-segment displays.
Figure 25 Connections
between the 7-segment display HEX0 and Cyclone IV E FPGA
|
Signal
Name |
FPGA
Pin No. |
Description
|
I/O
Standard |
|
HEX0[0]
|
PIN_G18
|
Seven
Segment Digit 0[0] |
2.5V |
|
HEX0[1]
|
PIN_F22
|
Seven
Segment Digit 0[1] |
2.5V |
|
HEX0[2]
|
PIN_E17
|
Seven
Segment Digit 0[2] |
2.5V |
|
HEX0[3]
|
PIN_L26
|
Seven
Segment Digit 0[3] |
Depending
on JP7 |
|
HEX0[4]
|
PIN_L25
|
Seven
Segment Digit 0[4] |
Depending
on JP7 |
|
HEX0[5]
|
PIN_J22
|
Seven
Segment Digit 0[5] |
Depending
on JP7 |
|
HEX0[6]
|
PIN_H22
|
Seven
Segment Digit 0[6] |
Depending
on JP7 |
|
HEX1[0]
|
PIN_M24
|
Seven
Segment Digit 1[0] |
Depending
on JP7 |
|
HEX1[1]
|
PIN_Y22
|
Seven
Segment Digit 1[1] |
Depending
on JP7 |
|
HEX1[2]
|
PIN_W21
|
Seven
Segment Digit 1[2] |
Depending
on JP7 |
|
HEX1[3]
|
PIN_W22
|
Seven
Segment Digit 1[3] |
Depending
on JP7 |
|
HEX1[4]
|
PIN_W25
|
Seven
Segment Digit 1[4] |
Depending
on JP7 |
|
HEX1[5]
|
PIN_U23
|
Seven
Segment Digit 1[5] |
Depending
on JP7 |
|
HEX1[6]
|
PIN_U24
|
Seven
Segment Digit 1[6] |
Depending
on JP7 |
|
HEX2[0]
|
PIN_AA25
|
Seven
Segment Digit 2[0] |
Depending
on JP7 |
|
HEX2[1]
|
PIN_AA26
|
Seven
Segment Digit 2[1] |
Depending
on JP7 |
|
HEX2[2]
|
PIN_Y25
|
Seven
Segment Digit 2[2] |
Depending
on JP7 |
|
HEX2[3]
|
PIN_W26
|
Seven
Segment Digit 2[3] |
Depending
on JP7 |
|
HEX2[4]
|
PIN_Y26
|
Seven
Segment Digit 2[4] |
Depending
on JP7 |
|
HEX2[5]
|
PIN_W27
|
Seven
Segment Digit 2[5] |
Depending
on JP7 |
|
HEX2[6]
|
PIN_W28
|
Seven
Segment Digit 2[6] |
Depending
on JP7 |
|
HEX3[0]
|
PIN_V21
|
Seven
Segment Digit 3[0] |
Depending
on JP7 |
|
HEX3[1]
|
PIN_U21
|
Seven
Segment Digit 3[1] |
Depending
on JP7 |
|
HEX3[2]
|
PIN_AB20
|
Seven
Segment Digit 3[2] |
Depending
on JP6 |
|
HEX3[3]
|
PIN_AA21
|
Seven
Segment Digit 3[3] |
Depending
on JP6 |
|
HEX3[4]
|
PIN_AD24
|
Seven
Segment Digit 3[4] |
Depending
on JP6 |
|
HEX3[5]
|
PIN_AF23
|
Seven
Segment Digit 3[5] |
Depending
on JP6 |
|
HEX3[6]
|
PIN_Y19
|
Seven
Segment Digit 3[6] |
Depending
on JP6 |
|
HEX4[0]
|
PIN_AB19
|
Seven
Segment Digit 4[0] |
Depending
on JP6 |
|
HEX4[1]
|
PIN_AA19
|
Seven
Segment Digit 4[1] |
Depending
on JP6 |
|
HEX4[2]
|
PIN_AG21
|
Seven
Segment Digit 4[2] |
Depending
on JP6 |
|
HEX4[3]
|
PIN_AH21
|
Seven
Segment Digit 4[3] |
Depending
on JP6 |
|
HEX4[4]
|
PIN_AE19
|
Seven
Segment Digit 4[4] |
Depending
on JP6 |
|
HEX4[5]
|
PIN_AF19
|
Seven
Segment Digit 4[5] |
Depending
on JP6 |
|
HEX4[6]
|
PIN_AE18
|
Seven
Segment Digit 4[6] |
Depending
on JP6 |
|
HEX5[0]
|
PIN_AD18
|
Seven
Segment Digit 5[0] |
Depending
on JP6 |
|
HEX5[1]
|
PIN_AC18
|
Seven
Segment Digit 5[1] |
Depending
on JP6 |
|
HEX5[2]
|
PIN_AB18
|
Seven
Segment Digit 5[2] |
Depending
on JP6 |
|
HEX5[3]
|
PIN_AH19
|
Seven
Segment Digit 5[3] |
Depending
on JP6 |
|
HEX5[4]
|
PIN_AG19
|
Seven
Segment Digit 5[4] |
Depending
on JP6 |
|
HEX5[5]
|
PIN_AF18
|
Seven
Segment Digit 5[5] |
Depending
on JP6 |
|
HEX5[6]
|
PIN_AH18
|
Seven
Segment Digit 5[6] |
Depending
on JP6 |
|
HEX6[0]
|
PIN_AA17
|
Seven
Segment Digit 6[0] |
Depending
on JP6 |
|
HEX6[1]
|
PIN_AB16
|
Seven
Segment Digit 6[1] |
Depending
on JP6 |
|
HEX6[2]
|
PIN_AA16
|
Seven
Segment Digit 6[2] |
Depending
on JP6 |
|
HEX6[3]
|
PIN_AB17
|
Seven
Segment Digit 6[3] |
Depending
on JP6 |
|
HEX6[4]
|
PIN_AB15
|
Seven
Segment Digit 6[4] |
Depending
on JP6 |
|
HEX6[5]
|
PIN_AA15
|
Seven
Segment Digit 6[5] |
Depending
on JP6 |
|
HEX6[6]
|
PIN_AC17
|
Seven
Segment Digit 6[6] |
Depending
on JP6 |
|
HEX7[0]
|
PIN_AD17
|
Seven
Segment Digit 7[0] |
Depending
on JP6 |
|
HEX7[1]
|
PIN_AE17
|
Seven
Segment Digit 7[1] |
Depending
on JP6 |
|
HEX7[2]
|
PIN_AG17
|
Seven
Segment Digit 7[2] |
Depending
on JP6 |
|
HEX7[3]
|
PIN_AH17
|
Seven
Segment Digit 7[3] |
Depending
on JP6 |
|
HEX7[4]
|
PIN_AF17
|
Seven
Segment Digit 7[4] |
Depending
on JP6 |
|
HEX7[5]
|
PIN_AG18
|
Seven
Segment Digit 7[5] |
Depending
on JP6 |
|
HEX7[6]
|
PIN_AA14
|
Seven
Segment Digit 7[6] |
3.3V |
Table 5 Pin
Assignments for 7-segment Displays
Memory
Controller and Programmer
The Control Panel can be
used to write/read data to/from the SDRAM, SRAM, EEPROM, and Flash chips on the
DE2-115 board. As an example, we will describe how the SDRAM may be accessed;
the same approach is used to access the SRAM, EEPROM, and Flash. Click on the
Memory tab and select “SDRAM” to reach the window in the figure below.
Figure 26 Accessing the
SDRAM
A 16-bit word can be
written into the SDRAM by entering the address of the desired location,
specifying the data to be written, and pressing the Write button. Contents of
the location can be read by pressing the Read button. Above figure depicts the
result of writing the hexadecimal value 06CA into offset address 200, followed
by reading the same location.
The Sequential Write
function of the Control Panel is used to write the contents of a file into the
SDRAM as follows:
1.
Specify the starting address in the Address box.
2.
Specify the number of bytes to be written in the
Length box. If the entire file is to be loaded, then a checkmark may be placed
in the File Length box instead of giving the number of bytes.
3.
To initiate the writing process, click on the Write
a File to Memory button.
4.
When the Control Panel responds with the
standard Windows dialog box asking for the source file, specify the desired
file in the usual manner.
The Control Panel also
supports loading files with a .hex extension. Files with a .hex extension are
ASCII text files that specify memory values using ASCII characters to represent
hexadecimal values. For example, a file containing the line
0123456789ABCDEF
Defines eight 8-bit values: 01, 23, 45, 67, 89,
AB, CD, EF. These values will be loaded consecutively
into the memory.
The Sequential Read
function is used to read the contents of the SDRAM and fill them into a file as
follows:
1.
Specify the starting address in the Address box.
2.
Specify the number of bytes to be copied into
the file in the Length box. If the entire contents of the SDRAM are to be
copied (which involves all 128 Mbytes), then place a checkmark in the Entire
Memory box.
3.
Press Load Memory Content to a File button.
4.
When the Control Panel responds with the
standard Windows dialog box asking for the destination file, specify the
desired file in the usual manner.
Users can use the similar way to access the SRAM, EEPROM and
Flash. Please note that users need to erase the Flash before writing data to
it.
USB
Monitoring
The Control Panel provides
users a USB monitoring tool which monitors the status of the USB devices
connected to the USB port on the DE2-115 board. By plugging in a USB device to
the USB host port of the board, the device type is displayed on the control
window. Below Figure shows a USB mouse plugged into the host USB port.
Figure 27 USB Mouse
Monitoring Tool
PS/2
Device
The Control Panel provides
users a PS/2 monitoring tool which monitors the real-time status of a PS/2
mouse connected to the DE2-115 board. The movement of the mouse and the status
of the three buttons will be shown in the graphical and text interface. The
mouse movement is translated as a position (x,y) with range from (0,0)~(1023,767). This function
can be used to verify the functionality of the PS/2 connection.
Follow the steps below to exercise the PS/2
Mouse Monitoring tool:
1.
Choosing the PS/2 tab leads to the window in the
Figure Below.
2.
Plug a PS/2 mouse to the PS/2 port on the
DE2-115 board.
3.
Press the Start button to start the PS/2 mouse
monitoring process, and the button caption is changed from Start to Stop. In
the monitoring process, the status of the PS/2 mouse is updated and shown in
the Control Panel’s GUI window in real-time. Press Stop to terminate the
monitoring process.
Figure 28 PS/2 Mouse
Monitoring Tool
SD
Card
The function is designed to
read the identification and specification information of the SD Card. The 4-bit
SD MODE is used to access the SD Card. This function can be used to verify the
functionality of the SD Card Interface. Follow the steps below to exercise the
SD Card:
1.
Choosing the SD Card tab leads to the window in
the figure below.
2.
Insert an SD Card to the DE2-115 board, and then
press the Read button to read the SD Card. The SD Card’s identification,
specification, and file format information will be displayed in the control
window.
Figure 29 Reading the SD
Card Identification and Specification
VGA
DE2-115 Control Panel
provides VGA pattern function that allows users to output color pattern to
LCD/CRT monitor using the DE2-115 board. Follow the steps below to generate the
VGA pattern function:
1.
Choosing the VGA tab leads to the window in the
figure below.
2.
Plug a D-sub cable to VGA connector of the
DE2-115 board and LCD/CRT monitor.
3.
The LCD/CRT monitor will display the same color
pattern on the control panel window.
4.
Click the drop down menu shown in the figure
below where you can output the selected color individually.
Figure 30 Controlling
VGA display
HSMC
Select the HSMC tab to
reach the window shown in the figure below. This function is designed to verify
the functionality of the signals located on the HSMC connector. Before running
the HSMC loopback verification test, follow the instruction noted under the
Loopback Installation section and click on Verify. Please note to turn off the
DE2-115 board before the HSMC loopback adapter is installed to prevent any
damage to the board.
Figure 31 HSMC loopback
verification test performed under Control Panel
RS-232
Communication
The Control Panel allows
users to verify the operation of the RS-232 serial communication interface on
the DE2-115. The setup is established by connecting a RS-232 9-pin male to
female cable from the PC to the RS-232 port where the Control Panel communicates
to the terminal emulator software on the PC, or vice versa. Alternatively, a
RS-232 loopback cable can also be used if you do not wish to use the PC to
verify the test. The Receive terminal window on the Control Panel monitors the
serial communication status. Follow the steps below to initiate the RS-232
communication:
1.
Choosing the RS-232 tab leads to the window in
the figure below.
2.
Plug in a RS-232 9-pin male to female cable from
PC to RS-232 port or a RS-232 loopback cable directly to RS-232 port.
3.
The RS-232 settings are provided below in case a
connection from the PC is used:
•
Baud Rate: 115200
•
Parity Check Bit: None
•
Data Bits: 8
•
Stop Bits: 1
•
Flow Control (CTS/RTS): ON
4.
To begin the communication, enter specific
letters followed by clicking Send. During the communication process, observe
the status of the Receive terminal window to verify its operation.
Figure 32 RS-232 Serial
Communication
Nios
II Processor
Nios II is a soft-core processor targeted for
Altera’s FPGA devices. As opposed to a fixed prefabricated processor, this
soft-core processor is described by HDL codes and then mapped onto FPGA’s
generic logic cells. Thus it can be configured and tuned by adding or removing
features to meet performance or cost goals. This approach offers more
flexibility.
There are three basic versions of Nios II in the SOPC Builder :
•
Nios II/f: The fast core is designed for optimal
performance. It has a 6-stage pipeline, instruction cache, data cache, and
dynamic branch prediction.
•
Nios II/s: The standard core is designed for small
size while maintaining good performance. It has a 5-stage pipeline, instruction
cache, and static branch prediction.
•
Nios II/e: The economy core is designed for optimal
size. It is not pipelined and contains no cache.
Figure 33 Nios II Processor Dialog
JTAG
UART Core
The JTAG UART (Universal
Asynchronous Receiver and Transmitter) core with Avalon interface provides a
method to communicate serial character streams between a host PC and the board.
On one side, the Nios II processor communicates with
the core by reading and writing control and data registers. To increase the
performance and regulate data transmission, a write FIFO buffer and a read FIFO
buffer are also included in this core. On the other side, the core uses the
JTAG circuitry built into Altera FPGA and provides host access via the JTAG
pins on the FPGA. The host PC can connect to the FPGA via any Altera JTAG
download cable, such as the USB-Blaster cable.
Figure 34 JTAG UART Core
Block Diagram
The software support for
the JTAG UART core is provided by Altera as well. For the Nios
II processor, device drivers are provided in the HAL (Hardware Abstraction
Layer) system library, allowing software to access the core using the ANSI C
Standard Library functions, such as getchar() and printf(). For the host PC, Altera provides JTAG terminal
software NIOS EDS that manages the connection to the target, decodes the JTAG
data stream, and displays characters on screen. The connection between a host
PC and an Nios II system
containing a JTAG UART core is shown below.
Figure 35 Host-Target
Connection
The JTAG UART core in our Nios II system is used to debug the software program. For
example, print out acceleration data or write image data into a file of the
host PC. In the SOPC Builder, this core is configured in default settings. In
our Nios II system, the size of Nios
II processor is not a problem so Nios II/f is selected
for optimal performance. The configuration dialog is displayed in Figure. In
addition, we also need to specify the memories and locations of the reset
vector and exception vector. A typical system usually adopts a nonvolatile
memory module for the reset code. Thus the Flash memory is selected as the
reset vector memory. Since our software program requires a relatively large
amount of memory, SRAM is adopted as the exception vector memory. The other
settings for our Nios II processor is default. Note
that a level-1 JTAG debug module is used in the default setting.
Communication
JTAG
Chain on DE2-115 Board
To use JTAG interface for
configuring FPGA device, the JTAG chain on DE2-115 must form a close loop that
allows Quartus II programmer to detect FPGA device.
Figure illustrates the JTAG chain on DE2-115 board. Shorting pin1 and pin2 on
JP3 can disable the JTAG signals on HSMC connector that will form a close JTAG
loop chain on DE2-115 board. Thus, only the on board FPGA device (Cyclone IV E)
will be detected by Quartus II programmer. If users
want to include another FPGA device or interface containing FPGA device in the
chain via HSMC connector, short pin2 and pin3 on JP3 to enable the JTAG signal
ports on the HSMC connector.
Figure 36 The JTAG chain
on DE2-115 board
Figure 37 The JTAG chain
configuration header
The sections below describe
the steps used to perform both JTAG and AS programming. For both methods the
DE2-115 board is connected to a host computer via a USB cable. Using this
connection, the board will be identified by the host computer as an Altera USB
Blaster device. The process for installing on the host computer the necessary
software device driver that communicates with the USB Blaster is described in
the tutorial “Getting Started with Altera’s DE2-115 Board” (tut_initialDE2-115.pdf).
This tutorial is available on the DE2-115 System CD.
Configuring the FPGA in JTAG Module
Figure illustrates the JTAG
configuration setup. To download a configuration bit stream into the Cyclone IV
E FPGA, perform the following steps:
•
Ensure that power is applied to the DE2-115
board
•
Configure the JTAG programming circuit by
setting the RUN/PROG slide switch (SW19) to the RUN position Connect the
supplied USB cable to the USB Blaster port on the DE2-115 board
•
The FPGA can now be programmed by using the Quartus II Programmer to select a configuration bit stream
file with the .sof filename extension
Figure 38 The JTAG
configuration scheme